Patents by Inventor Ali Salih

Ali Salih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160172458
    Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.
    Type: Application
    Filed: February 10, 2016
    Publication date: June 16, 2016
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Mark Griswold, Ali Salih
  • Publication number: 20160118490
    Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.
    Type: Application
    Filed: September 14, 2015
    Publication date: April 28, 2016
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji PADMANABHAN, Prasad VENKATRAMAN, Zia HOSSAIN, Chun-Li LIU, Jason MCDONALD, Ali SALIH, Alexander YOUNG
  • Publication number: 20160099314
    Abstract: In one embodiment, a method of forming an MOS transistor includes forming a threshold voltage (Vth) of the MOS transistor to have a first value at interior portions of the MOS transistor and a second value at other locations within the MOS transistor that are distal from the interior portion wherein the second value is less than the first value.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 7, 2016
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Kirk HUANG, Chun-Li LIU, Ali SALIH
  • Patent number: 9299776
    Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: March 29, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Zia Hossain, Ali Salih
  • Publication number: 20160064325
    Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ali SALIH, Chun-Li LIU, Gordon M. GRIVNA
  • Patent number: 9268887
    Abstract: A system and method for determining fluid flow of compressible and non-compressible liquids includes an input receiving an object model defined as a plurality of cells having nodes, a processor and memory. The processor is configured for: discretizing a partial differential equation (PDE) corresponding to the received model; for each node P: (i) locating all neighboring cells that share the node P; establish a finite difference stencil at each cell center, and identify stencil intersection points with cell boundary edges; calculate an approximate solution of the PDE at the intersection points; (ii) approximating the PDE at the cell center of the neighboring cells using the stencil and discretized PDE; and (iii) updating a solution of the PDE at the node P by using the solution of approximated discretized PDE at all the neighboring cell centers; and iteratively updating the solution for all nodes P from an initial guess until a convergence criterion is satisfied.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 23, 2016
    Assignee: UNIVERSITY OF WINDSOR
    Inventors: Ronald Barron, Ali Salih, James Jianmin Situ
  • Patent number: 9263598
    Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: February 16, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Mark Griswold, Ali Salih
  • Publication number: 20160043178
    Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes providing a semiconductor material having a surface, forming an epitaxial layer of carbon doped semiconductor material on the semiconductor substrate, the epitaxial layer having a surface, forming a nucleation layer on the epitaxial layer; and forming a layer of III-nitride material on the nucleation layer. In accordance with another embodiment, the semiconductor component includes a silicon semiconductor substrate of a first conductivity type; a carbon doped epitaxial layer on the silicon semiconductor substrate; a buffer layer over the carbon doped buffer layer; and a channel layer on the buffer layer.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 11, 2016
    Inventors: Chun-Li Liu, Ali Salih
  • Publication number: 20160043219
    Abstract: In accordance with an embodiment, a method for manufacturing a semiconductor component includes forming a first trench through a plurality of layers of compound semiconductor material. An insulating material is formed on first and second sidewalls of the first trench and first and second sidewalls of the second trench and a trench fill material is formed in the first and second trenches. In accordance with another embodiment, the semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 11, 2016
    Inventors: Chun-Li Liu, Balaji Padmanabhan, Ali Salih, Peter Moens
  • Publication number: 20160043181
    Abstract: An electronic device can transistor having a channel layer that includes a compound semiconductor material. In an embodiment, the channel layer overlies a semiconductor layer that includes a carrier barrier region and a carrier accumulation region. The charge barrier region can help to reduce the likelihood that de-trapped carriers from the channel layer will enter the charge barrier region, and the charge accumulation region can help to repel carriers in the channel layer away from the charge barrier layer. In another embodiment, a barrier layer overlies the channel layer. Embodiments described herein may help to produce lower dynamic on-resistance, lower leakage current, another beneficial effect, or any combination thereof.
    Type: Application
    Filed: June 17, 2015
    Publication date: February 11, 2016
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chun-Li LIU, Ali SALIH
  • Patent number: 9214423
    Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: December 15, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ali Salih, Chun-Li Liu, Gordon M. Grivna
  • Publication number: 20150340482
    Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 26, 2015
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji PADMANABHAN, John Michael PARSEY, JR., Ali SALIH, Prasad VENKATRAMAN
  • Patent number: 9129889
    Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: September 8, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, John Michael Parsey, Jr., Ali Salih, Prasad Venkatraman
  • Publication number: 20150236172
    Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Mark Griswold, Ali Salih
  • Publication number: 20150108569
    Abstract: In an embodiment, a method of forming a semiconductor may include forming a plurality of active trenches and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches. The method may also include forming at least one active trench of the plurality of active trenches having corners linking trench ends to sides of active trenches wherein each active trench of the plurality of active trenches has a first profile along the first length and a second profile at or near the trench ends; and forming a termination trench substantially surrounding an outer periphery of the plurality of active trenches and having a second profile wherein one of the first profile or the second profile includes a non-linear shape.
    Type: Application
    Filed: June 5, 2014
    Publication date: April 23, 2015
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. GRIVNA, Zia HOSSAIN, Ali SALIH
  • Publication number: 20140264369
    Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 18, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Balaji PADMANABHAN, John Michael PARSEY, JR., Ali Salih, Prasad Venkatraman
  • Publication number: 20140264449
    Abstract: In one embodiment, a HEMT semiconductor device includes an isolation region that may include oxygen wherein the isolation region may extend thorough an ALGaN and GaN layer into an underlying layer.
    Type: Application
    Filed: January 23, 2014
    Publication date: September 18, 2014
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: John Michael Parsey, JR., Chun-Li Liu, Balaji Padmanabhan, Ali Salih
  • Publication number: 20140264456
    Abstract: In an embodiment, a semiconductor device is formed by a method that includes, providing a base substrate of a first semiconductor material, and forming a layer that is one of SiC or a III-V series material on the base substrate. In a different embodiment, the base substrate may be one of silicon, porous silicon, or porous silicon with nucleation sites formed thereon, or silicon in a (111) plane.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ali Salih, John Michael Parsey, JR.
  • Publication number: 20140264452
    Abstract: In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.
    Type: Application
    Filed: February 6, 2014
    Publication date: September 18, 2014
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Ali Salih, Chun-Li Liu, Gordon M. Grivna
  • Patent number: 8431959
    Abstract: In one embodiment, a bi-directional ESD device is formed to have a third harmonic at frequencies no less than about one gigahertz wherein the third harmonic has a magnitude that is no greater than about minus thirty five dBm.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: April 30, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: T. Jordan Davis, Ali Salih