Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes.

Abstract: In one embodiment, a temperature compensated current source includes a depletion mode transistor coupled in series with an active semiconductor device that adjust the depletion mode transistor to minimize variations in the current due to temperature changes.

Abstract: In one embodiment, a two terminal multi-channel ESD device is configured to include a zener diode and a plurality of P-N diodes.

Abstract: In one embodiment, a plurality of ESD devices are used to form an integrated semiconductor filter circuit. Additional diodes are formed in parallel with the ESD structures in order to increase the input capacitance.

Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode.

Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.

Abstract: A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event.

Abstract: A transient voltage suppressor and a method for protecting against surge and electrostatic discharge events. A semiconductor substrate of a first conductivity type has gate and anode regions of a second conductivity type formed therein. A PN junction diode is formed from a portion of the gate region and the semiconductor substrate. A cathode is formed adjacent to another portion of the gate region. A thyristor is formed from the cathode, the gate region, the substrate, and the anode region. Zener diodes are formed from other portions of the gate region and the semiconductor substrate. A second Zener diode has a breakdown voltage that is greater than a breakdown voltage of a first Zener diode and that is greater than a breakover voltage of the thyristor. The first Zener diode protects against a surge event and the second Zener diode protects against an electrostatic discharge event.

Abstract: Transient voltage suppressor and method for manufacturing the transient voltage suppressor having a dopant or carrier concentration in a portion of a gate region near a Zener region that is different from a dopant concentration in a portion of a gate region that is away from the Zener region.

Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.

Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P? region is disposed under the P+ region. The P? region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P? region may be disposed adjacent to a first portion of the P+ region while another P? region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the substrate, to provide a layer offset (28) between the driver device area and power device area. An epi region of uniform thickness is formed over the driver device and power device areas. A portion of the epi layer is removed to provide another layer offset (70). An oxide layer (68) of uniform thickness is formed over the epi region. The oxide layer is planarized to remove oxide layer over the N+ layer. An oxide-filled trench (80) is formed between the driver device and the power device. The oxide-filled trench extends down to the oxide layer to isolate the driver device from the power device.

Abstract: A junction field effect transistor (JFET) has a gate region, drain region, and a source region. An epitaxial region having a first conductivity type is disposed over the drain region. The first conductivity type is N-type semiconductor material. The gate region is disposed within a trench which is formed in the epitaxial region. A P+ region is disposed within the epitaxial region and under the gate region. The P+ region has a first doping concentration of a second conductivity type opposite the first conductivity type. A P? region is disposed under the P+ region. The P? region has a second doping concentration of the second conductivity type which is less than the first doping concentration. The P? region may be disposed adjacent to a first portion of the P+ region while another P? region is disposed adjacent to a second portion of the P+ region. The P+ region may be implanted from the gate region deep into the epitaxial region.