Abstract: Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

Abstract: Methods and systems for reducing AM/PM distortion in a polar amplifier are disclosed and may comprise adding an offset signal to an amplitude signal in the digital domain and removing the offset signal in the analog domain during polar modulation. A sum of an amplitude signal and an offset signal may be mixed with a phase signal in a first differential amplifier to generate a first voltage signal, and the offset signal may be mixed with the phase signal in a second differential amplifier to generate a second voltage signal, which may be subtracted from the first voltage signal. The amplitude and offset signals may be mixed with the phase signal by modulating a current in the differential amplifiers, which may comprise cascode differential amplifiers. The modulated current may be generated using a current source and a current mirror circuit, which may comprise a cascode current mirror.

Abstract: A polar transmitter includes a digital processor coupled to receive a complex modulated digital signal and a feedback signal produced from the complex modulated digital signal and that is operable to compare the complex modulated digital signal to the feedback signal to determine an error signal indicative of a difference between the complex modulated digital signal and the feedback signal. The digital processor is further operable to produce a correction signal from the error signal and to add the correction signal to the complex modulated digital signal to produce a corrected complex modulated digital signal.

Abstract: A polar transmitter includes a digital processor for producing a phase correction signal and a complex modulated digital signal including a digital phase-modulated signal. The phase correction signal is added to the digital phase-modulated signal to produce a corrected digital phase signal. The corrected digital phase signal is input to a phase-locked loop (PLL) to produce an RF phase signal that tracks the phase of the digital phase-modulated signal based on the corrected digital phase signal.

Abstract: A radio frequency (RF) transmitter front-end includes a digital to analog conversion module and a power amplifier module. The digital to analog conversion module is coupled to convert amplitude information into analog amplitude adjust signals when a first mode is active and is coupled to convert power level information into analog power level signals when a second mode is active. The power amplifier module is coupled to amplify first phase modulated RF signals in accordance with the analog amplitude adjust signals to produce first outbound RF signals when the first mode is active and is coupled to amplify second phase modulated RF signals in accordance with the analog power level signals to produce second outbound RF signals when the second mode is active.

Abstract: A digital to analog conversion (DAC) module includes a digital to analog converter, a sample and hold circuit, and a switch module. The digital to analog converter is coupled to convert a digital signal into an analog signal. The sample and hold circuit is coupled to sample the analog signal to produce a sampled analog signal. The switch module is coupled to provide the analog signal as an output of the DAC module when the DAC module in a first mode and to output the analog signal to the sample and hold circuit when the DAC module in a second mode, wherein the sampled analog signal provides the output of the DAC module in the second mode.

Abstract: Methods and systems for fast calibration to cancel phase feedthrough are disclosed and may comprise individually activating each of n binary-weighted cells utilizing a control signal in a power amplifier driver (PAD) and measuring the output signal, or offset, in response to a null signal applied to an input of each binary-weighted cell. This offset may be fed back, summed, and adjusted until the measured PAD output may be minimized. This calibrated offset may cancel phase feedthrough of the PAD, and the calibrated offset for each binary-weighted cell may be stored in a lookup table. The control signal may also be utilized for controlling the output power of the PAD by activating appropriate binary-weighted cells. For each of the 2n output powers, a calibrated offset is calculated utilizing a weighted sum of the stored offsets for the activated binary-weighted cells.

Abstract: A method for regulating a voltage in an integrated circuit device includes providing a first regulated output based upon a first voltage input range and subsequently receiving the first regulated output and providing a second regulated output based upon a second voltage input range of the first regulated output. A circuit is further provided that operates accordingly. Additionally, a clipper circuit is provided at the input to protect for over voltage conditions that may results, for example, from a charging battery to cause an output voltage of the battery to substantially exceed ordinary output voltage levels.

Abstract: Methods and apparatus for calibrating a transitional loop, such as a phase locked loop, are disclosed. An example method includes performing an open loop calibration of a voltage controlled oscillator (VCO). The open loop calibration includes tuning the output oscillation frequency of the VCO to within a predetermined range of frequencies. The example method further includes determining a voltage offset and a gain error of an analog to digital converter (ADC) coupled with the phase locked loop. The example method also includes determining a gain offset of the open loop calibrated VCO using the voltage offset and the gain error of the ADC. In the example method, a signal provided by a charge pump of the PLL is adjusted based on the determined gain offset.

Abstract: Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

Abstract: Methods and apparatus for calibrating a transitional loop, such as a phase locked loop, are disclosed. An example method includes performing an open loop calibration of a voltage controlled oscillator (VCO). The open loop calibration includes tuning the output oscillation frequency of the VCO to within a predetermined range of frequencies. The example method further includes determining a voltage offset and a gain error of an analog to digital converter (ADC) coupled with the phase locked loop. The example method also includes determining a gain offset of the open loop calibrated VCO using the voltage offset and the gain error of the ADC. In the example method, a signal provided by a charge pump of the PLL is adjusted based on the determined gain offset.

Abstract: A differential amplifier is configured in a cascode configuration that includes input transistors that are connected to corresponding cascode transistors. The gates of the cascode transistors are tied together to form a common bias for the cascode devices. The input transistors of the differential amplifier receive a differential input signal that is amplified and outputted to an output circuit that is connected to the cascode transistors. The cascode devices require a bias voltage for proper operation. Preferably, the bias voltage puts the cascode devices into the saturation region. The gates of cascode devices are coupled together and connected to a bias terminal. In embodiments of the invention, the bias terminal is connected to another terminal of the chip to provide the bias for the cascode devices. This can include the input and output nodes if they have a well-defined and relatively fixed voltage.

Abstract: Various embodiments are disclosed relating to wireless systems, and also relating to transmitter amplifiers, such as, for example, polar transmitter amplifiers with variable output power. According to an example embodiment, a circuit is provided including a plurality of selectable amplifier cells. Each amplifier cell may receive a phase or frequency modulated signal and an amplitude modulated signal. Each amplifier cell may output a signal based upon a combination of the received amplitude modulated signal and the received phase or frequency modulated signal if the amplifier cell is selected. The circuit may provide a variable output current or output power based upon the selection of one or more of the amplifier cells.

Abstract: Various embodiments are disclosed relating to wireless transmitters, and also relating to multi-band transformers. According to an example embodiment, an apparatus may include a multi-band transformer configured to receive as an input a signal associated with a first frequency band or a signal associated with a second frequency band. The transformer may include one or more inputs and a first output and a second output. The transformer may also include one or more switches coupled to the transformer and configured to selectively output a received input signal onto the first output and/or the second output of the transformer.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

Abstract: Aspects of a method and system for digital to analog conversion for power amplifier driver amplitude modulation are presented. Various aspects of the system may include circuitry that enables oversampling, within a single integrated circuit device, of each of a plurality of samples in a digital baseband signal. The circuitry may enable reduction of a number of bits, i.e., coarse quantization, in each of the oversampled plurality of samples so as to cause displacement of the quantization noise that occurred as a result of the coarse quantization. A subsequent signal may be generated based on the oversampled signal. The circuitry may enable the subsequent signal to be low-pass filtered utilizing filter circuitry in the single integrated circuit device, thereby attenuating the quantization noise displaced into the higher frequency range of the oversampled signal.

Abstract: Various embodiments are disclosed relating to power control techniques for wireless transmitters. In an example embodiment, an apparatus is provided that may include a digital-to-analog converter (DAC) adapted to convert a digital amplitude signal to an analog amplitude signal during a first transmission mode and adapted to convert a digital power level signal to an analog power level signal during a second transmission mode.

Abstract: An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block. The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. A power down input signal can also be received that allows the circuit to be powered down.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

Abstract: A differential amplifier is configured in a cascode configuration that includes input transistors that are connected to corresponding cascode transistors. The gates of the cascode transistors are tied together to form a common bias for the cascode devices. The input transistors of the differential amplifier receive a differential input signal that is amplified and outputted to an output circuit that is connected to the cascode transistors. The cascode devices require a bias voltage for proper operation. Preferably, the bias voltage puts the cascode devices into the saturation region. The gates of cascode devices are coupled together and connected to a bias terminal. In embodiments of the invention, the bias terminal is connected to another terminal of the chip to provide the bias for the cascode devices.