Abstract: Systems and methods disclosed herein provide for variable data width memory. For example, in accordance with an embodiment of the present invention, a technique for doubling a width of a memory is disclosed, without having to increase a width of the internal data path or the number of input/output pads.

Abstract: A method for balancing cells or groups of cells connected in parallel and in series for a battery pack by providing a continuously balanced state of charge while in a discharge phase, a charge phase, a quiescent phase, a storage phase, or combinations of these phases.

Abstract: A battery pack control module for balancing a plurality of cells or groups of cells connected in series includes a controller assembly, a disconnect circuit, a pack sensing circuit, a balancing circuit, and computer instructions for instructing the controller assembly to control the disconnect circuit and the balancing circuit. The disconnect circuit engages the controller assembly and a plurality of cells or groups of cells connected in series. The pack sensing circuit connects to the controller assembly and the plurality of cells or groups of cells connected in series. The balancing circuit connects between the plurality of cells or groups of cells connected in series, and engages the controller assembly. The plurality of cells or groups of cells connected in series is balanced when the battery pack control module operates in a charging phase, a discharging phase, a quiescent phase, or a storage phase.

Abstract: Systems and methods provide bit line coupling detection techniques for multi-port memory applications. For example, in accordance with an embodiment of the present invention, a memory includes at least one column of memory having a plurality of memory cells and at least two ports and a dummy column having a dummy memory cell and a first port and a second port. At least one bit line is provided for each port of the columns of memory and the dummy column, with the dummy column adapted to provide a read timing indication by performing a write operation through the first port at substantially the same time as a read operation through the second port.

Abstract: Systems and methods are disclosed herein to provide techniques for writing to certain bits of a word location in a memory. For example, in accordance with an embodiment of the present invention, a method of implementing byte enable logic for a memory is disclosed, with the byte enable logic signals provided on one or more address lines.

Abstract: A method for extending the power duration of lithium ion cells or groups of lithium ion cells connected in parallel and in series by providing a continuously balanced state of charge while in a discharge phase, a charge phase, a quiescent phase, a storage phase, or combinations of these phases.

Abstract: In accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of memory blocks, and a plurality of continuation routing paths associated with the memory blocks. A plurality of continuation multiplexers, coupled to the continuation routing paths, are adapted to route signals between the memory blocks, between the logic blocks, and/or between the memory blocks and the logic blocks.

Abstract: Methods, apparatus and articles facilitate the loading of a set of new instructions to replace set of existing instructions on a processor based device, for example an automatic data collection device. For example, a new operating system may replace an existing operating system using an executable that disables interrupts and/or exceptions. The new operating system may execute with, or without booting. The set of new instructions may be fragmented to fit the block size of a nonvolatile programmable memory, and/or may be compressed. Validation values such as check sums and/or error correction may be employed.

Abstract: A drill bit for drilling through earthen formations and forming a borehole. In an embodiment, the bit comprises a bit body having a bit axis. In addition, the bit comprises a plurality of cone cutters, each of the cone cutters being mounted on the bit body and adapted for rotation about a different cone axis. Further, at least one cone cutter on the bit comprises an array of cutter elements mounted in a band. Still further, the cutter elements in the array are mounted in a plurality of differing radial positions relative to the bit axis.

Abstract: Systems and methods provide sense amplifier timing techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of memory cells and a sense amplifier that provides a sense amplifier output signal based on data provided by the plurality of memory cells, with the sense amplifier output signal provided under control of a sense amplifier enable signal. A delay control circuit provides a delay to the sense amplifier enable signal based on a value provided by at least one configuration fuse.

Abstract: In accordance with one embodiment of the present invention, a programmable logic device includes at least one block of memory having a plurality of memory cells and a plurality of fuses adapted to provide a first set of signals that determines a first configuration for the at least one block of memory. A plurality of multiplexers are adapted to select the first set of signals from the plurality of fuses to configure the at least one block of memory in the first configuration or a second set of signals to configure the at least one block of memory in a second configuration.

Abstract: A flashlight having a non-conductive housing, an electric power source, a light source, and two nodes disposed on external surfaces of the non-conductive housing, wherein the flashlight is adapted to allow electric current to flow from the power source through the light source when both of the two nodes are abutted by a user's hand, activating the flashlight without further manipulation required by the user. Inadvertent activation of the flashlight is minimized by including a protruding rib between the nodes or by disposing the nodes on different sides of the flashlight.

Abstract: Systems and methods are disclosed herein to provide improved address decoding techniques for memory. For example, in accordance with an embodiment of the present invention, an integrated circuit includes an address register that receives a reset signal, a clock signal, and an address signal and provides a registered address signal. The registered address signal provides at least a true and a complement signal, with the true and complement signal set to approximately the same logical value upon assertion of the reset signal. An address pre-decoder, coupled to the address register, at least partially decodes the registered address signal to provide a pre-decoded output signal. A wordline driver, coupled to the address pre-decoder, receives a wordline enable signal and the pre-decoded output signal and provides a wordline signal based on the pre-decoded output signal upon assertion of the wordline enable signal.

Abstract: A safety device for lithium ion cells or groups of lithium ion cells connected in parallel and in series by providing a continuously balanced state of charge while in a discharge phase, a charge phase, a quiescent phase, a storage phase, or combinations of these phases.

Abstract: Systems and methods provide output data from a memory. For example, in accordance with an embodiment of the present invention, techniques are disclosed for providing glitch-free output data from a memory through feedback of the output data signal.

Abstract: Systems and methods are disclosed for memory, including techniques for reading and writing to memory. For example, in accordance with an embodiment of the present invention, a method of implementing a read and a write operation (e.g., a read before write operation) is disclosed for a memory, such as for example for a single port or a multiport memory, with the write operation beginning prior to the completion of the read operation.

Abstract: Systems and methods provide sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier for a memory array is disclosed having an associated precharge circuit and a read completion detection circuit.

Abstract: Systems and methods including sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier for a memory array having an associated precharge circuit and a read completion detection circuit.

Abstract: Systems and methods to provide sense amplifiers for various applications. For example, in accordance with an embodiment of the present invention, a sense amplifier is disclosed having an associated precharge circuit and a read completion detection circuit.