Patents by Inventor Allen McTeer
Allen McTeer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10504911Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.Type: GrantFiled: May 8, 2019Date of Patent: December 10, 2019Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Allen McTeer
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Publication number: 20190362785Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.Type: ApplicationFiled: May 20, 2019Publication date: November 28, 2019Inventors: Yongjun Jeff Hu, Tsz W. Chan, Christopher W. Petz, Everett Allen McTeer
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Publication number: 20190360120Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.Type: ApplicationFiled: June 10, 2019Publication date: November 28, 2019Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen Mcteer
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Publication number: 20190355902Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.Type: ApplicationFiled: February 4, 2019Publication date: November 21, 2019Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Publication number: 20190333933Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (h) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.Type: ApplicationFiled: June 4, 2019Publication date: October 31, 2019Applicant: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
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Patent number: 10446727Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.Type: GrantFiled: January 5, 2017Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
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Publication number: 20190267390Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.Type: ApplicationFiled: May 8, 2019Publication date: August 29, 2019Applicant: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Allen McTeer
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Patent number: 10381072Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.Type: GrantFiled: April 30, 2014Date of Patent: August 13, 2019Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Tsz W. Chan, Christopher W. Petz, Everett Allen McTeer
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Patent number: 10361216Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.Type: GrantFiled: September 20, 2017Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
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Patent number: 10344398Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.Type: GrantFiled: January 6, 2016Date of Patent: July 9, 2019Assignee: Micron Technology, Inc.Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
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Patent number: 10325653Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.Type: GrantFiled: December 28, 2017Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Tsz W. Chan, Christopher W. Petz, Everett Allen McTeer
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Patent number: 10325917Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.Type: GrantFiled: August 24, 2017Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Allen McTeer
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Publication number: 20190140023Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.Type: ApplicationFiled: January 7, 2019Publication date: May 9, 2019Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
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Publication number: 20190097017Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Publication number: 20190088671Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (h) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.Type: ApplicationFiled: September 20, 2017Publication date: March 21, 2019Inventors: Jordan D. Greenlee, John Mark Meldrim, E. Allen McTeer
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Publication number: 20190088867Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall.Type: ApplicationFiled: January 29, 2018Publication date: March 21, 2019Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Patent number: 10224479Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.Type: GrantFiled: January 29, 2018Date of Patent: March 5, 2019Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
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Patent number: 10177198Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.Type: GrantFiled: June 5, 2017Date of Patent: January 8, 2019Assignee: Micron Technology, Inc.Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
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Patent number: 10164044Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.Type: GrantFiled: April 16, 2015Date of Patent: December 25, 2018Assignee: Micron Technology, Inc.Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
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Patent number: 10079340Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.Type: GrantFiled: April 4, 2016Date of Patent: September 18, 2018Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer