Abstract: Photonic nanostructures, light absorbing apparatuses, and devices are provided. The photonic nanostructures include a plurality of photonic nanobars configured to collectively absorb light over an excitation wavelength range. At least two of the photonic nanobars of the plurality have lengths that are different from one another. Each photonic nanobar of the plurality has a substantially small width and a substantially small height relative to the different lengths. A method for forming such may comprise forming a plurality of first photonic nanobars comprising a width and a height that are smaller than a length of the plurality of first photonic nanobars, and forming a plurality of second photonic nanobars comprising a width and a height that are smaller than a length of the second photonic nanobar, wherein the lengths of the plurality of first photonic nanobars and the lengths of the plurality of second photonic nanobars are different from one another.

Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.

Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.

Abstract: Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.

Abstract: Method and apparatus for sputter depositing silver selenide and controlling defect formation in and on a sputter deposited silver selenide film are provided. A method of forming deposited silver selenide comprising both alpha and beta phases is further provided. The methods include depositing silver selenide using sputter powers of less than about 200 W, using sputter power densities of less than about 1 W/cm2, using sputter pressures of less than about 40 mTorr and preferably less than about 10 mTorr, using sputter gasses with molecular weight greater than that of neon, using cooling apparatus having a coolant flow rate at least greater than 2.5 gallons per minute and a coolant temperature less than about 25° C., using a magnetron sputtering system having a magnetron placed a sufficient distance from a silver selenide sputter target so as to maintain a sputter target temperature of less than about 350° C. and preferably below about 250° C.

Abstract: Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.

Abstract: Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.

Abstract: A method of forming a transistor gate construction includes forming a gate stack comprising a sacrificial material received over conductive gate material. The gate stack has lateral sidewalls having insulative material received there-against. The sacrificial material is removed from being received over the conductive gate material to form a void space between the insulative material over the conductive gate material. Elemental tungsten is selectively deposited within the void space over the conductive gate material and a transistor gate construction forming there-from is formed there-from, and which has a conductive gate electrode which includes the conductive gate material and the elemental tungsten. The transistor gate might be used in NAND, DRAM, or other integrated circuitry.

Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.

Abstract: Method and apparatus for sputter depositing silver selenide and controlling defect formation in and on a sputter deposited silver selenide film are provided. A method of forming deposited silver selenide comprising both alpha and beta phases is further provided. The methods include depositing silver selenide using sputter powers of less than about 200 W, using sputter power densities of less than about 1 W/cm2, using sputter pressures of less than about 40 mTorr and preferably less than about 10 mTorr, using sputter gasses with molecular weight greater than that of neon, using cooling apparatus having a coolant flow rate at least greater than 2.5 gallons per minute and a coolant temperature less than about 25° C., using a magnetron sputtering system having a magnetron placed a sufficient distance from a silver selenide sputter target so as to maintain a sputter target temperature of less than about 350° C. and preferably below about 250° C.

Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100?x composition. According to another embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between chalcogenide glass layers and further having a silver layer above at least one of said chalcogenide glass layers and a conductive adhesion layer above said silver layer.

Abstract: Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed.

Abstract: A method of forming an intermediate semiconductor device is disclosed that comprises providing a semiconductor substrate, forming a photoresist layer on the semiconductor substrate, implanting a dopant into the semiconductor substrate, and removing a dopant-containing layer from the photoresist layer. The dopant-containing layer includes dopant residuals and a carbon-rich crust and may be formed during implantation. The dopant-containing layer may be removed from the photoresist layer by exposing the dopant-containing layer to a water rinse, a chlorinated plasma or to a fluorinated plasma. The water rinse may include deionized water that is maintained at a temperature that ranges from approximately 25° C. to approximately 80° C. The fluorinated plasma may be formed from a gaseous precursor selected from the group consisting of nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, hexafluoroethane, sulfur hexafluoride, and mixtures thereof.

Abstract: The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to one embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between two glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a GexSe100-x composition. According to another embodiment of the invention, a resistance variable memory element is provided having at least one silver-selenide layer in between chalcogenide glass layers and further having a silver layer above at least one of said chalcogenide glass layers and a conductive adhesion layer above said silver layer.

Abstract: A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer passivates the copper layer surface and enhances the thermal conductivity of a semiconductor substrate by radiating heat from the substrate as well as from the copper layer.

Abstract: Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.

Abstract: The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one implementation, a method of depositing silver onto a metal selenide-comprising surface includes providing a deposition chamber comprising a sputtering target and a substrate to be depositing upon. The target comprises silver, and the substrate comprises an exposed surface comprising metal selenide. Gaseous cesium is flowed to the target and a bombarding inert sputtering species is flowed to the target effective to sputter negative silver ions from the target. The sputtered negative silver ions are flowed to the exposed metal selenide-comprising surface effective to deposit a continuous and completely covering silver film on the exposed metal selenide of the substrate.

Abstract: Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.

Abstract: Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion species to non-impurity-based ion species in a plasma generated by the plasma doping process and a ratio of each impurity-based ion species to a total impurity-based ion species in the plasma are directly measured. The ratios may be directly measured by ion mass spectroscopy. The total ion dose and the ratios are used to determine the total impurity dose. The apparatus includes an ion detector, an ion mass spectrometer, a dosimeter, and software.