Abstract: A method of etching a substrate that includes: generating a first plasma from a first gas flowing into a first chamber by applying a first power pulse to a first electrode located in the first chamber over a first time duration; and forming a recess in a substrate located in a second chamber, the forming including: providing radicals from the first chamber into the second chamber; applying a plurality of second power pulses to a second electrode located in the second chamber during a second time duration to generate a second plasma in the second chamber from a second gas flowing into the second chamber, the first chamber being pressurized higher than the second chamber; and applying a plurality of third power pulses to a third electrode located in the second chamber during a third time duration to accelerate ions of the second plasma.

Abstract: In one exemplary embodiment, described herein is an ALE process for etching an oxide. In one embodiment, the oxide is silicon oxide. The ALE modification step includes the use of a carbon tetrafluoride (CF4) based plasma. This modification step preferentially removes oxygen from the surface of the silicon oxide, providing a silicon rich surface. The ALE removal step includes the use of a hydrogen (H2) based plasma. This removal step removes the silicon enriched monolayer formed in the modification step. The silicon oxide etch ALE process utilizing CF4 and H2 steps may be utilized in a wide range of substrate process steps. For example, the ALE process may be utilized for, but is not limited to, self-aligned contact etch steps, silicon fin reveal steps, oxide mandrel pull steps, oxide spacer trim, and oxide liner etch.

Abstract: A method for plasma processing includes: sustaining a plasma in a plasma processing chamber, the plasma processing chamber including a first radio frequency (RF) electrode and a second RF electrode, where sustaining the plasma includes: coupling an RF source signal to the first RF electrode; and coupling a bias signal between the first RF electrode and the second RF electrode, the bias signal having a bipolar DC (B-DC) waveform including a plurality of B-DC pulses, each of the B-DC pulses including: a negative bias duration during which the pulse has negative polarity relative to a reference potential, a positive bias duration during which the pulse has positive polarity relative to the reference potential, and a neutral bias duration during which the pulse has neutral polarity relative to the reference potential.

Abstract: A method of plasma processing includes cyclically performing a cycle including the steps of performing a glow phase and performing an afterglow phase. The glow phase includes providing a first SP pulse comprising a first SP power level for a first duration to an SP electrode to generate a capacitively coupled plasma in a plasma processing chamber. The first SP pulse terminates at the end of the glow phase. The afterglow phase is performed after the glow phase and includes providing a BP pulse train to a BP electrode coupled to a target substrate within the plasma processing chamber in an afterglow of the capacitively coupled plasma for a second duration between about 10 ?s and about 100 ?s. The BP pulse train includes a plurality of BP spikes. Each of the plurality of BP spikes is a DC pulse that has a first BP power level.

Abstract: A method for treating a substrate includes receiving the substrate in a vacuum process chamber. The substrate includes a III-V film layer disposed on the substrate. The III-V film layer includes an exposed surface, an interior portion underlying the exposed surface, and one or more of the following: Al, Ga, In, N, P, As, Sb, Si, or Ge. The method further includes altering the chemical composition of the exposed surface and a fraction of the interior portion of the III-V film layer to form an altered portion of the III-V film layer using a first plasma treatment, removing the altered portion of the III-V film layer using a second plasma treatment, and repeating the altering and removing of the III-V film layer until a predetermined amount of the III-V film layer is removed from the substrate.

Abstract: A method for forming a semiconductor device includes depositing a metal resist layer over a layer to be patterned that is formed over a substrate; patterning the metal resist layer using a lithography process to form a patterned metal resist layer and expose portions of the layer to be patterned; selectively depositing a silicon containing layer over the patterned resist layer by exposing the substrate to a gas mixture comprising a silicon precursor, the silicon containing layer being preferentially deposited over a top surface of the metal resist layer; and performing a surface cleaning process by exposing the layer to be patterned and the patterned metal resist layer covered with the silicon containing layer to a plasma process with an etch chemistry comprising a halogen or hydrogen.

Abstract: A plasma processing apparatus includes an antenna configured to generate plasma of a processing gas in a chamber. The antenna includes: an inner coil provided around the gas supply unit to surround a gas supply unit; and an outer coil provided around the gas supply unit and the inner coil to surround them. The outer coil is configured such that both ends of a wire forming the outer coil are opened; power is supplied from a power supply unit to a central point of the wire; the vicinity of the central point of the wire is grounded; and the outer coil resonates at a wavelength that is a half of a wavelength of the high frequency power. The inner coil is configured such that both ends of a wire forming the inner coil are connected through a capacitor and the inner coil is inductively coupled with the inner coil.

Abstract: In certain embodiments, a method of processing a semiconductor structure includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed over a substrate. The method includes patterning the copper layer, using the patterned layer as an etch mask, by performing a cyclic etch process to form a recess in the copper layer. The cyclic etch process includes forming, in a first etch step, a passivation layer on an exposed surface of the copper layer by exposing the exposed surface of the copper layer to a chlorine gas. The passivation layer replaces at least a portion of a surface layer of the copper layer. The cyclic etch process includes subsequently etching, in a second etch step, the passivation layer using a first plasma that includes a noble gas. Each cycle of the cyclic etch process extends the recess in the copper layer.

Abstract: A method includes performing a first on phase including applying an SP pulse to an SP electrode to generate plasma, performing a second on phase after the first on phase, performing a corner etch phase after the second on phase, and performing a by-product management phase after the corner etch phase. The SP pulse terminates at the end of the first on phase. The second on phase includes applying a first BP pulse to a BP electrode coupled to a target substrate. The first BP pulse includes a first BP power level and accelerates ions of the plasma toward to target substrate. The corner etch phase includes applying a BP spike including a second BP power level greater than the first BP power level. The duration of the BP spike is less than the duration of the first BP pulse.

Abstract: A method of optimizing a recipe for a plasma process includes (a) building a virtual metrology (VM) model that predicts a wafer characteristic resulting from the plasma process based on a plasma parameter and (b) building a control model that describes a relationship between the plasma parameter and a recipe parameter. (c) The wafer characteristic is measured after performing the plasma process according to the recipe. (d) Whether the wafer characteristic is within a predetermined range is determined. (e) The VM model and the control model are calibrated based on the wafer characteristic. (f) The recipe is optimized by updating the plasma parameter based on the wafer characteristic using the VM model and updating the recipe parameter based on the plasma parameter using the control model. (c), (d), (e) and (f) are repeated until the wafer characteristic is within the predetermined range.

Abstract: A method for processing a substrate includes performing a cyclic plasma etch process including a plurality of cycles, where each cycle of the plurality of cycles includes: causing chemical reactions with the surface of the substrate by exposing a surface of the substrate to fluorine radicals extracted from a first gas discharge plasma formed using a first gaseous mixture including a non-polymerizing fluorine compound; cooling the substrate and concurrently removing residual gaseous byproducts by flowing a second gaseous mixture over the substrate, and at the same time, suppressing the chemical reactions with the surface of the substrate; and performing a plasma surface modification process by exposing the surface of the substrate to hydrogen radicals extracted from a second gas discharge plasma formed using a third gaseous mixture including gases including nitrogen and hydrogen.

Abstract: A method for processing a substrate includes performing a cyclic plasma process including a plurality of cycles, each cycle of the plurality of cycles including purging a plasma processing chamber including the substrate with a first deposition gas including carbon. The substrate includes a first layer including silicon and a second layer including a metal oxide. The method further includes exposing the substrate to a first plasma generated from the first deposition gas to selectively deposit a first polymeric film over the first layer relative to the second layer; purging the plasma processing chamber with an etch gas including fluorine; and exposing the substrate to a second plasma generated from the etch gas to etch the second layer.

Abstract: A plasma processing apparatus includes a plasma processing chamber, a source power coupling element configured to generate plasma in an interior of the plasma processing chamber by coupling source power to the plasma processing chamber, a DC pulse generator configured to generate a DC pulse train at a DC pulse frequency, a substrate holder disposed in the interior of the plasma processing chamber, a DC coupling element coupled to the DC pulse generator, a DC current path including the DC coupling element, the plasma, and a reference potential node in a series configuration, the DC coupling element being configured to bias the substrate holder relative to the reference potential node using the DC pulse train, and a capacitive pre-coat layer disposed between the DC coupling element and the plasma. The capacitive pre-coat layer increases the RC time constant of the DC current path according to the DC pulse frequency.

Abstract: In certain embodiments, a method of processing a semiconductor structure includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed over a substrate. The method includes patterning the copper layer, using the patterned layer as an etch mask, by performing a cyclic etch process to form a recess in the copper layer. The cyclic etch process includes forming, in a first etch step, a passivation layer on an exposed surface of the copper layer by exposing the exposed surface of the copper layer to a chlorine gas. The passivation layer replaces at least a portion of a surface layer of the copper layer. The cyclic etch process includes subsequently etching, in a second etch step, the passivation layer using a first plasma that includes a noble gas. Each cycle of the cyclic etch process extends the recess in the copper layer.

Abstract: A plasma processing system includes a radical source chamber including a gas inlet, an electrode coupled to a radio frequency (RF) power source, where the electrode is configured to generate radicals within the radical source chamber, and an exit for radicals generated within the radical source chamber; a plenum attached to the exit of the radical source chamber, where the plenum is made of a first thermal conductor, and where the walls of the plenum include openings for gas flow; and a process chamber connected to the radical source chamber through the plenum. The process chamber includes a substrate holder disposed below the plenum; a gas outlet below the substrate holder; and process chamber walls including a second thermal conductor, where the process chamber walls of the process chamber are thermally coupled to the walls of the plenum.

Abstract: In an example, a method includes depositing a first sidewall spacer layer over a substrate having a layer stack including alternating layers of a nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the first sidewall spacer layer formed over the dummy gate. The method includes depositing a metal-containing liner over the first sidewall spacer layer; forming a first sidewall spacer along the dummy gate by anisotropically etching the metal-containing liner and the first sidewall spacer layer; performing an anisotropic etch back process to form a plurality of vertical recesses in the layer stack; laterally etching the layer stack and form a plurality of lateral recesses between adjacent nanosheets; depositing a second sidewall spacer layer to fill the plurality of lateral recesses; and etching a portion of the second sidewall spacer layer to expose tips of the nanosheet layers.

Abstract: Various embodiments of systems and methods are described herein for controlling a pulsed plasma. Pulse timing parameters (e.g., the pulse on-time and/or the pulse-off time) of the plasma generation source may be controlled based on the measurement data received from measurement device(s), to control the plasma exposure of the substrate during a sequence of dynamically controlled pulses within the plasma process chamber. In addition or alternatively, pulse timing parameters (e.g., the pulse on-time and/or the pulse-off time) can be applied to the source power, bias power, and/or both based on the measurement data received from measurement device(s), to control a plasma exposure of the substrate. The pulse timing changes may be made in a feedforward or feedback manner.

Abstract: A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.

Abstract: A method for manufacturing a FET semiconductor structure includes providing a substrate comprising at least one source/drain contact of at least one FET, the at least one source/drain contact formed adjacent to a dummy gate of the at least one FET. A TiSi2 film with C54 structure is selectively deposited directly on and fully covering the at least one source/drain contact relative to a vertical sidewall of a gate spacer between the at least one source/drain contact and the dummy gate. The dummy gate is replaced with a replacement metal gate.

Abstract: A plasma processing apparatus includes an antenna configured to generate plasma of a processing gas in a chamber. The antenna includes: an inner coil provided around the gas supply unit to surround a gas supply unit; and an outer coil provided around the gas supply unit and the inner coil to surround them. The outer coil is configured such that both ends of a wire forming the outer coil are opened; power is supplied from a power supply unit to a central point of the wire; the vicinity of the central point of the wire is grounded; and the outer coil resonates at a wavelength that is a half of a wavelength of the high frequency power. The inner coil is configured such that both ends of a wire forming the inner coil are connected through a capacitor and the inner coil is inductively coupled with the inner coil.