Abstract: Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with reduced number of processing. A controller receives first and second program voltage (PV) levels associated with read operations on cells. The controller estimates first and second probability distribution parameter sets representing skew normal distributions of the first and second PV levels, respectively. The controller estimates an optimal read threshold voltage based on the first and second probability distribution parameter sets. The optimal read threshold voltage is a read threshold voltage such that first probability density function (PDF) value of the skew normal distribution of the first PV level is the same as the second PDF value of the skew normal distribution of the second PV level.

Abstract: Embodiments provide a scheme for estimating an optimal read threshold voltage using a deep neural network (DNN) with a reduced number of processing. A controller includes a combined neural network, which receives first and second cumulative distribution function (CDF) values, each CDF value corresponding to a program voltage (PV) level associated with a read operation on the cells. The combined neural network generates first and second connection vectors based on the first and second CDF values and first weight values, and estimates an optimal read threshold voltage based on the first and second connection vectors and second weight values.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes performing, based on a plurality of read voltages, read operations on each of a plurality of pages of a memory device, determining, based on the read operations for each page of the plurality of pages, a ones count in each page and a checksum of an error correcting code for each page, generating a first estimator for the checksum and a second estimator for the ones count based on a polynomial regression, determining, based on the first estimator and the second estimator, an updated plurality of read voltages, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device.

Abstract: A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages.

Abstract: Embodiments provide a scheme for non-parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller is configured to: generate multiple optimal read threshold voltages corresponding to multiple sets of two cumulative distribution function (CDF) values, respectively; perform read operations on the cells using a plurality of read threshold voltages; generate cumulative mass function (CMF) samples based on the results of the read operations; receive first and second CDF values, selected from among a plurality of CDF values, each CDF value corresponding to each CMF sample; and estimate an optimal read threshold voltage corresponding to the first and second CDF values, among the multiple optimal read threshold voltages.

Abstract: Techniques related to a low-power, low-memory multiply and accumulate (MAC) unit are described. In an example, the MAC unit performs a MAC operation that represents a multiplication of numbers. At least the bit representation of one number is compressed based on a quantization and a clustering of quantization values, whereby index bits are used instead of the actual bit representation. The index bits are loaded in an index buffer and a bit representation of another number is loaded in an input buffer. The index bits are used in a lookup to determine whether the corresponding bit representation and shift operations are applied to the input buffer based on this bit representation, followed by accumulation operations.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes performing, based on a plurality of read voltages, read operations on each of a plurality of pages of a memory device, determining, based on the read operations for each page of the plurality of pages, a ones count in each page and a checksum of an error correcting code for each page, generating a first estimator for the checksum and a second estimator for the ones count based on a polynomial regression, determining, based on the first estimator and the second estimator, an updated plurality of read voltages, and applying the updated plurality of read voltages to the memory device to retrieve information from the memory device.

Abstract: Devices, systems and methods for improving a decoding operation in a non-volatile memory are described. An example method includes performing a first hard read to obtain a first set of values stored in a plurality of cells, storing the first set of values in a first buffer, performing a plurality of subsequent hard reads on the plurality of cells to obtain a plurality of subsequent sets of values, performing, for each subsequent set of values, the following operations: computing a quality metric, storing, in a second buffer, a difference between the subsequent set of values and the set of values stored in the first buffer, wherein the difference is stored in a compressed format, and storing, in response to the quality metric exceeding a threshold, the subsequent set of values in the first buffer, and generating, based on the first buffer and the second buffer, the log-likelihood ratio.

Abstract: Embodiments of the present disclosure provide a scheme for decoding over a small subgraph which highly likely includes some errors. A controller is configured to: control the first decoder to decode the data, read from the memory device, using a parity check matrix for the error correction code; extract one or more subgraphs from the entire bipartite graph of the parity check matrix, which is defined by a plurality of variable nodes and a plurality of check nodes when a particular condition satisfied; and control the second decoder to decode the decoding result of the first decoder using a submatrix of the parity check matrix corresponding to the extracted subgraphs.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: Embodiments provide a scheme for parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller performs read operations on cells using read threshold voltages; generates CMF samples based on the read operations; and receives first and second CDF values, which correspond to CMF samples, each CDF value representing a skew normal distribution. The controller estimates first and second probability distribution parameter sets corresponding to the first and second CDF values, respectively; determines first and second PDF values using the first and second probability distribution parameter sets, respectively; and estimates, as an optimal read threshold voltage, a read threshold voltage corresponding to a cross-point of the first and second PDF values.

Abstract: A descrambler receives data from a memory device. The descrambler calculates a sub-syndrome weight for multiple bits in each of the plurality of descrambled sequences using a set parity check matrix to generate multiple sub-syndrome weights, one for each of the plurality of descrambled sequences. The descrambler selects a sub-syndrome weight among the multiple sub-syndrome weights. The descrambler determines, as a correct scrambler sequence for descrambling the data, a scrambler sequence corresponding to the selected sub-syndrome weight, among the plurality of scrambler sequences.

Abstract: Embodiments provide a scheme for parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller performs read operations on cells using read threshold voltages; generates CMF samples based on the read operations; and receives first and second CDF values, which correspond to CMF samples, each CDF value representing a skew normal distribution. The controller estimates first and second probability distribution parameter sets corresponding to the first and second CDF values, respectively; determines first and second PDF values using the first and second probability distribution parameter sets, respectively; and estimates, as an optimal read threshold voltage, a read threshold voltage corresponding to a cross-point of the first and second PDF values.

Abstract: A controller optimizes read retry thresholds for a memory device using one or more previous reads and a condition. The controller determines a read level table based on a condition indicative of a state of the memory device and selects an entry among multiple entries in the selected read level table based on a historical read threshold. For the selected entry, the controller: determines fail bits for data associated with multiple read operations on the cells using multiple read retry thresholds; and determines an order of the multiple read retry thresholds based on the fail bits determination.

Abstract: Devices, systems, and methods for detecting and mitigating oscillations in a bit-flipping decoder associated with a non-volatile memory are described. An example method includes receiving a noisy codeword based on a transmitted codeword generated from a low-density parity-check code, performing a first plurality of decoding iterations on the noisy codeword, which comprises performing a message passing algorithm in a first order, computing, based on a completion of the first plurality of decoding iterations, a plurality of checksum values and a plurality of bit flip counts corresponding to the first plurality of decoding iterations, determining that the plurality of checksum values and the plurality of bit flip counts are periodic with a period less than a predetermined threshold, and performing a subsequent decoding iteration on the noisy codeword, the subsequent decoding iteration comprising performing the message passing algorithm in a second order different from the first order.

Abstract: Methods and apparatuses for generating optimized LDPC codes are proposed. One of the methods is a method for generating an optimized LDPC code for an asymmetric transmission channel. The method includes receiving an initial LDPC code for the asymmetric transmission channel. Further, the method includes performing a density evolution threshold optimization for the initial LDPC code in order to obtain the optimized LDPC code for the asymmetric transmission channel. A uniformly mixed symmetric channel density for the asymmetric transmission channel is used in the density evolution threshold optimization.

Abstract: Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device, generating, based on the plurality of cell counts and the plurality of read voltages, at least one ones count, at least one checksum, and a plurality of samples corresponding to a distribution function of at least one read voltage of the plurality of read voltages, determining an updated value for the at least one read voltage based on an output of a deep neural network whose input comprises the at least one ones count, the at least one checksum, and the plurality of samples, and applying the updated value of the at least one read voltage to the memory device to retrieve information from the memory device.

Abstract: A method is provided for determining log-likelihood ratio (LLR) for soft decoding based on information obtained from hard decoding, in a storage system configured to perform hard decoding and soft decoding of low-density parity-check (LDPC) codewords. The method includes performing hard decoding of codewords in a page, the hard decoding including a first hard read and one or more re-reads using predetermined hard read threshold voltages, and grouping memory cells in the page into a plurality of bins based on the read threshold voltages for the first hard read and the one or more re-reads. The method also includes computing parity checksum and one's count for memory cells in each bin, and determining LLR for each bin of memory cells based on read data, checksums, and one's count for each bin.

Abstract: Devices, systems and methods for improving the performance of a memory device are described. An example method includes obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device, generating, based on the plurality of cell counts and the plurality of read voltages, at least one ones count, at least one checksum, and a plurality of samples corresponding to a distribution function of at least one read voltage of the plurality of read voltages, determining an updated value for the at least one read voltage based on an output of a deep neural network whose input comprises the at least one ones count, the at least one checksum, and the plurality of samples, and applying the updated value of the at least one read voltage to the memory device to retrieve information from the memory device.