Abstract: Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a first encoder and a second encoder. The first encoder encodes, based on a constrained code, a first group of data to generate a third group of data, the first group of data corresponding to first and third logical pages among a plurality of logical pages. The second encoder encodes, based on a Gray code, a second group of data and the third group of data to generate encoded sequences corresponding to a plurality of program-voltage (PV) levels, the second group of data corresponding to the second and fourth logical pages among the plurality of logical pages.

Abstract: Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when writing data to a superblock of the memory, a wordline of the superblock stores “D+P” parity bits that protect “D” data bits of a codeword having a length of “2D+P.” Other wordlines of the superblock store codewords each having a length of “D+P” (e.g., “D” data bits and “P” parity bits). If the decoding of any of these codewords of length “D+P” fails, the “D+P” parity bits are used to re-decode the failed wordline.

Abstract: Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Abstract: A system includes memory cells arranged in blocks and a memory controller. The memory controller receives a read command to read a first block. The first block can be associated with a first read count and a first read threshold. The first read count is incremented when the first block is read, and when the first read count reaches the read threshold, a read reclaim test is performed. The first read count is set to zero after a power off or a read reclaim operation. When the first read count is zero, an adaptive read threshold is selected based on the number of bit errors. Further, in a read reclaim test, the number of bit errors is tested against an adaptive error threshold to determine whether a garbage collection operation is performed.

Abstract: Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability.

Abstract: Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.

Abstract: A memory system, a controller including a bit-flipping (BF) decoder and a min-sum (MS) decoder that may be included in the memory system and operating methods thereof in which the controller determines a quality metric as a function of initial syndrome weight and information of the BF decoder after a set number of decoding iterations by the BF decoder in a test period. After the test period, the controller applies the quality metric to each codeword to determine whether to send that codeword first to the BF decoder for decoding or directly to the MS decoder for decoding.

Abstract: A memory system, a bit-flipping (BF) low-density parity check (LDPC) decoder included in the memory system and operating methods thereof in which such decoder or decoding has a reduced error floor. Such a BF LDPC decoder is configured using a deep learning framework of trained and training neural networks and data separation that exploits the degree distribution information of the constructed LDPC codes.

Abstract: A system includes a plurality of memory cells. Each memory cell is programmed to a data state corresponding to one of multiple cell programmed voltages. The memory cells are read to determine a programmed data state of each memory cell. Error correction decoding is performed to determine a corrected data state of each memory cell. The corresponding cell levels, or programmed voltages, are determined based on the programmed data state and the corrected data state. A first error count represents a total number of error cells that have a higher cell level for the corrected data state than the programmed data state. A second error count represents a total number of error cells that have a lower cell level for the corrected data state than the programmed data state. The system is configured to perform a memory operation based on the first error count and the second error count.

Abstract: Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.

Abstract: A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.

Abstract: Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a min-sum decoding approach that monitors whether two values received in messages from two variable nodes connected to a check nodes are equal and are the minimum value among the values received by the check nodes from other variable nodes connected thereto. Upon detecting such an event, the minimum value is adjusted by reducing it by an adjustment value to generate an adjusted minimum value. This adjusted minimum value approximates the minimum value that a sum-product algorithm (SPA) decoding approach would have generated. The adjusted minimum value is included in a response message sent from the check node to a variable node. The bit corresponding to that variable node is decoded based on this adjusted minimum value.

Abstract: A method is provided for controlling a storage system, which can include a plurality of memory cells arranged in blocks and a memory controller coupled to the plurality of memory cells for controlling data write and read in the plurality of memory cells. The method includes identifying a block as a good block, if a count of bad pages in the block is zero, identifying the block as a degraded block if the count of bad pages is below a threshold number, and identifying the block as a bad block if the count of bad pages is above or equal to the threshold number. The method includes using good blocks and degraded blocks for read and program operations, and not using the bad blocks.

Abstract: A dynamic interleaver performs a read operation to identify bit lines with high failures, and form groups of data bits for parity bits computation, such that each group includes at most one data bit from the bit lines with high failures. Thus, the interleave selects the bit lines with high failures based on a most recent read test, and can be adjusted according to the conditions of the storage device.

Abstract: An apparatus of a semiconductor memory system and an operating method thereof include: a plurality of memory devices; and a controller coupled with the memory devices, the controller including a training data storage, a classifier trainer, and a decoder, is configured to perform decoding iterations, wherein the training data storage configured to collect and store at least training data, the classifier trainer configured to train classifiers at least with the training data, and the decoder configured to decode code-bits in accordance with rules of the classifier.

Abstract: A storage system includes memory cells arranged in an array and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to perform a read operation in response to a read command from a host, perform a first soft decoding of data from the read operation using existing LLR (log likelihood ratio) values stored in the memory controller, update existing LLR values using LLR values from neighboring memory cells and existing weight coefficients that account for influence from the neighboring memory cells. The memory controller is also configured to perform a second soft decoding using the updated LLR values. If the second soft decoding is successful, the memory controller performs a recursive update of weight coefficients to reflect updated influence from neighboring memory cells and stores the updated weight coefficient in the memory controller for use in further decoding.

Abstract: A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.

Abstract: Adaptive read-threshold schemes for a memory system determine read-threshold with the lowest BER/UECC failure-rates while continuing to serve the host-reads with the required QoS. When it is determined that the QoS or other quality metric is not met for a particular read-threshold, which may be an initial, default, read-threshold, the performance of other read-thresholds are estimated. These estimates may then be used to determine an optimal read-threshold. During the iterative process, selection variables, e.g., how many times, and for which read commands, to use each of the non-default read-thresholds in future read-attempts may be determined on-the-fly.

Abstract: Decoder is provided for memory systems. The decoder receives data from a memory device including a plurality of pages, each storing data, and decoding the data based on a type of a page in which the data is stored, among the plurality of pages and life cycle information indicating a current state of the memory device in its life cycle.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.