Abstract: Memory controllers, decoders and methods to perform decoding of user bits and parity bits including those corresponding to low degree variable nodes. For each of the user bits, the decoder performs a variable node update operation and a check node update operation for connected check nodes. After all of the user bits are processed, the decoder performs a parity node update operation for the parity bits using results of the variable node and check node update operations performed on the user bits.

Abstract: Memory controllers, decoders and methods execute a hybrid decoding scheme with exchange of information between multiple decoders. A first type of decoder performs initial decoding of a codeword when an unsatisfied check (USC) count of the codeword is less than a threshold, and a second type of decoder performs decoding of a codeword when the USC count of the codeword is greater than or equal to the threshold. During decoding by one of the decoders, the controller generates information from an output of that decoder and send the information to the other decoder, which the other decoders uses in decoding. The codeword is routed and rerouted between the decoders, which may include a q-bit bit-flipping (q-BF) decoder and a min-sum (MS) decoder, based on conditions that occur during decoding.

Abstract: Disclosed are devices, systems and methods for improving performance of a block of a memory device. In an example, performance is improved by implementing soft chipkill recovery to mitigate bitline failures in data storage devices. An exemplary method includes encoding each horizontal row of cells of a plurality of memory cells of a memory block to generate each of a plurality of codewords, and generating a plurality of parity symbols, each of the plurality of parity symbols based on diagonally positioned symbols spanning the plurality of codewords.

Abstract: Decoder is provided for memory systems. The decoder receives data from a memory device including a plurality of pages, each storing data, and decoding the data based on a type of a page in which the data is stored, among the plurality of pages and life cycle information indicating a current state of the memory device in its life cycle.

Abstract: Techniques are described for improving the decoding latency and throughput of an error correction system that includes multiple decoders. For example, the error correction system intelligently distributes and balances the decoding of codewords between the different decoders. In particular, the error correction system can consider different factors associated with decoding various codewords including, for instance, the checksum of a codeword that is to be decoded, an estimated number of decoding iterations to decode the codeword by a decoder based on the checksum, and/or an accumulated number of decoding iterations for decoding by the decoder of the codeword in addition to other codewords already buffered for the decoder. Given these factors, the error correction system can generate a decision to decode the codeword by the decoder or by another decoder of the error correction system, where the decision optimizes the performance.

Abstract: Memory controllers, decoders and methods execute a hybrid decoding scheme. An initial iteration of decoding of a codeword is performed using a bit-flipping (BF) decoder or a min-sum (MS) decoder depending on whether or not an unsatisfied check (USC) count of the codeword is less than a threshold. For this initial iteration, the BF decoder is used when the USC count is less than the threshold, and MS decoder when the USC count is greater than or equal to the threshold. When decoding of the codeword is initially performed with the BF decoder, decoding continues with the BF decoder until a first set of conditions is satisfied or the codeword is successfully decoded. When decoding of the codeword is performed with the MS decoder, decoding continues with the MS decoder until a second set of conditions is satisfied.

Abstract: Error recovery operations are provided for a memory system. The memory system includes a memory device including a plurality of cells and a controller. The controller performs a read on a select cell among the plurality of cells. The controller adjusts a log-likelihood ratio (LLR) value on the select cell to generate an adjusted LLR value, based on first read data on the select cell and second read data on at least one neighbor cell adjacent to the select cell, when the read on the select cell fails.

Abstract: Encoders and decoders are provided for memory systems. An encoder scrambles data bits corresponding to a logical page, selected from among multiple logical pages, using a plurality of random sequences, to generate a plurality of scrambled sequences; selects, as an encoded sequence, a scrambled sequence among the plurality of scrambled sequences; and provides a memory device with the encoded sequence to store the encoded sequence in multiple level cells. The selected scrambled sequence has the lowest number of logical high values among the plurality of scrambled sequences.

Abstract: Devices and methods that generate code on chip-kill parity in which the code is generated and shortened using variable node degree information for improved decoding of data. In one aspect, memory controller comprises an encoder configured to construct a first code of D data bits and P parity bits, determine the number of distinct variable degree nodes L and the number of data bits of each of the variable degree nodes in the first code, and construct a second code that is shorter than the first code based on the determined number of variable degree nodes and the number of data bits of each of the variable degree nodes in the first code.

Abstract: Memory systems, controllers, decoders and methods execute decoding with a mufti-level interference correction scheme. A decoder performs first soft decoding to generate log likelihood ratio (LLR) values of a select bit and bits of memory cells neighboring a memory cell of the select bit. A quantizer obtains an estimated LLR value of the select bit based on the LLR values of the select bit and the bits of the memory cells neighboring the memory cell of the select bit, when the first soft decoding fails. The decoder performs second soft decoding using the estimated LLR value when the first soft decoding fails, and performs third soft decoding using information obtained from application of a deep learning model to provide a more accurate estimate of the LLR value of the select bit when the second soft decoding fails.

Abstract: Techniques for profiling storage blocks in non-transitory memory (e.g., flash memory dies) to determine their retention capability, and assigning them with labels based on retention, are described. A superblock (SB) can be formed from physical blocks with the same labels located in different dies. The disclosed system and methods improve storage efficiency when the update frequency of stored data is non-uniform, as is typically the case. Moreover, the disclosed embodiments improve the reliability of solid state drives (SSDs), as well as reduce data refresh frequency and write amplification due to periodic refresh. A storage system can comprise a controller configured to obtain expected retention times for a plurality of storage blocks. The controller can partition the blocks into superblocks based on the retention times. A respective superblock is associated with a superblock retention time range, and contains blocks having expected retention times within the retention time range.

Abstract: Encoding methods and systems are provided for a memory device including quadruple-level cell (QLC) memory cells. A controller of a memory system includes a constrained encoding device including a first encoder and a second encoder. The first encoder jointly encodes, based on a constrained code, two data bits corresponding to two logical pages, selected from among multiple logical pages. The second encoder independently encodes, based on an error-correction code, the encoded data bits and remaining data bits to generate symbols corresponding to a plurality of program-voltage (PV) levels, the remaining data bits corresponding to two non-selected logical pages among the multiple logical pages.

Abstract: Soft read suspend schemes for a memory system reduce overall command latency and improve QoS of the memory system, which includes a memory device and a memory controller. The memory controller controls the memory device to perform, in response to a command, a hard read to generate hard information for hard decoding, and predict whether soft decoding of the data is to be performed, and if so, how many soft reads are to be performed. When hard decoding fails and soft decoding and at least one soft read is to be performed, the memory device is controlled to perform an initial soft read to generate soft information for soft decoding, predict whether, and if so, how many, subsequent soft reads are to be performed, and determine whether to perform a first subsequent soft read on the data based on the prediction.

Abstract: Methods and systems are provided for performing a garbage collection scheme for hybrid address mapping. A controller of a memory system receives data and a logical address for the data from a host device, writes the data in a page of an open log block and performs a garbage collection on a log block and under a certain condition, one or more data blocks, when the open log block is full.

Abstract: A low density parity check (LDPC) decoding device includes a data generator for generating information with a first precision; a data converter for converting the information into a message with a second precision greater than the first precision; and a decoding processor for performing a low density parity check (LDPC) decoding using the message to generate decoded data.

Abstract: Methods and systems are provided for an address mapping scheme using a hash table. A controller of a memory system partitions a plurality of physical blocks included in a memory device into a plurality of data blocks and a plurality of log blocks, translates a logical address to a physical address based on a block-level mapping scheme or a page-level mapping scheme using a hash table, and performs a read and/or write operation based on the translated physical address.

Abstract: A storage system includes memory cells arranged in an array and a memory controller coupled to the memory cells for controlling operations of the memory cells. The memory controller is configured to perform a read operation in response to a read command from a host, perform a first soft decoding of data from the read operation using existing LLR (log likelihood ratio) values stored in the memory controller, update existing LLR values using LLR values from neighboring memory cells and existing weight coefficients that account for influence from the neighboring memory cells. The memory controller is also configured to perform a second soft decoding using the updated LLR values. If the second soft decoding is successful, the memory controller performs a recursive update of weight coefficients to reflect updated influence from neighboring memory cells and stores the updated weight coefficient in the memory controller for use in further decoding.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: Adaptive read-threshold schemes for a memory system determine read-threshold with the lowest BER/UECC failure-rates while continuing to serve the host-reads with the required QoS. When it is determined that the QoS or other quality metric is not met for a particular read-threshold, which may be an initial, default, read-threshold, the performance of other read-thresholds are estimated. These estimates may then be used to determine an optimal read-threshold. During the iterative process, selection variables, e.g., how many times, and for which read commands, to use each of the non-default read-thresholds in future read-attempts may be determined on-the-fly.