Patents by Inventor Ambreesh Bhattad

Ambreesh Bhattad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140210440
    Abstract: Circuits and methods to achieve a clean start-up process and power saving of pulsed enabled electronic devices having an output capacitor and components requiring biasing during normal operating conditions are disclosed. These electronic devices could be e.g. LDOs, amplifiers or buffers. A set of switches are enabling bias currents from the output capacitor to internal nodes requiring biasing under normal operational conditions as e.g. output nodes of amplifying means.
    Type: Application
    Filed: February 1, 2013
    Publication date: July 31, 2014
    Applicant: DIALOG SEMICONDUCTOR GMBH
    Inventors: Ambreesh Bhattad, Ludmil Nikolov
  • Publication number: 20140210430
    Abstract: Circuits and methods to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit are disclosed as e.g. a LDO or an amplifier. In a preferred embodiment of the disclosure is applied to an LDO. Modification of the resistive voltage divider ratio caused by the feed-forward capacitor during start-up is prevented while the voltage level of a voltage access point of the voltage divider on the feed-forward capacitor is maintained. Embodiments of the disclosure presented comprise using a start-up buffer or a start-up capacitor during the start-up phase.
    Type: Application
    Filed: February 1, 2013
    Publication date: July 31, 2014
    Applicants: DIALOG SEMICONDUCTOR B.V., DIALOG SEMICONDUCTOR GMBH
    Inventors: Ambreesh Bhattad, Ludmil Nikolov, Marinus Wilhelmus Kruiskamp
  • Publication number: 20140103893
    Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Applicant: DIALOG SEMICONDUCTOR GMBH
    Inventors: Ambreesh Bhattad, Ludmil Nikolov