Abstract: A regulator for providing a load current at a regulator output voltage to a load at an output of the regulator is described. The regulator has a differential input stage to provide a differential output voltage based on a reference voltage and based on the regulator output voltage. Furthermore, the regulator has an output driver to generate a control signal based on the differential output voltage. In addition, the regulator has a pass transistor to provide the load current in dependence of the control signal. The regulator also has clamping circuitry to sense an overvoltage indication which indicates that the pass transistor is being turned off. Furthermore, the clamping circuitry clamps the differential output voltage to a clamping voltage, if the overvoltage indication indicates that the pass transistor is being turned off.

Abstract: A voltage regulator is described. It includes an amplification stage to control a voltage level of a first gain node and of a second gain node in response to an input voltage, to activate a first and a second output stage, respectively. It further includes the first output stage to source a current at an output node of the voltage regulator from a first potential. The voltage regulator includes the second output stage to sink a current at the output node to a second potential. The voltage regulator includes a first operating point control circuit to set the voltage level of the first gain node such that a first maintenance current is sourced by the first output stage; and/or a second operating point control circuit to set the voltage level of the second gain node such that a second maintenance current is sunk by the second output stage.

Abstract: An LDO circuit with a current sink stage reduces significantly overshooting of the output voltage due to sudden changes of output current. The activation of the current sink stage is independent of the overshoot percentage of the regulated output voltage. The disclosure doesn't require large output capacitors to avoid the possibility of brownouts of chips supplied by the LDO.

Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.

Abstract: A low dropout (LDO) regulator with a limited startup inrush current is disclosed. The LDO includes a power source, error amplifier, pass transistor, feedback network, and a current limit control whose input is electrically connected to the pass transistor and the electrical output of the error amplifier and whose output limits current during startup. The LDO can include a current control limit comparator including a power source, and output of the pass transistor. The LDO can also include a bypass mode current control limit comparator having a first input voltage of the error amplifier, and a second input voltage from the error amplifier.

Abstract: A power providing circuit which is configured to provide a current at an output voltage to a load at an output of the power providing circuit is described. The power providing circuit comprises a power transistor which is configured to draw the current from a supply voltage, wherein a resistance of the power transistor is controlled using a control voltage which is applied to a control port of the power transistor. Furthermore, the power providing circuit comprises short circuit protection circuitry which is configured to couple the control port of the power transistor with a first port of the power transistor to put the power transistor in an off-state, subject to a drop of the output voltage.

Abstract: Circuits and methods to control current through a device biasing an output device in case the supply voltage is not higher than the output voltage are disclosed. The circuits and methods are applicable to e.g. LDOs, amplifiers, or buffers. A control loop detects if the supply voltage is not higher than the output voltage and regulates the drain-source voltage of the biasing device. The disclosure reduces power consumption in a driver stage in case the supply voltage is not higher than the output voltage.

Abstract: Circuits and methods to reduce the size of output capacitors of LDOs or amplifiers are disclosed. Nonlinear mirroring of the load current allows scaling of gain or adapting small signal impedance of a pass transistor depending on other inputs, in case of a preferred embodiment, allows to reduce small signal impedance at the gate of the pass transistor as the load current increases, hence allowing to reduce the size of an output capacitor without compromising stability of the system.

Abstract: An overshoot reduction circuit within a low dropout voltage regulator eliminates an overshoot at an output terminal resulting from a transient fault condition occurring at an input or output terminal. The overshoot reduction circuit monitors to sense if there is a transient fault condition occurring at the input or output terminal and provides a Miller capacitance at the output terminal of a differential amplifier of the low dropout voltage regulator to prevent the output of the differential amplifier from being discharged to ground during the transient. A control loop circuit balances current within an active load of the differential amplifier to clamp the output of the differential amplifier to its normal operating point. When the transient fault condition ends, the output voltage of the differential amplifier is set such that a pass transistor of the low dropout regulator responds quickly to resume the regulation to reduce or eliminate the overshoot.

Abstract: A dual mode low dropout voltage regulator has a low dropout regulation mode and a bypass mode and provides a smooth transition between mode transitions taking place under load. When an accessory requires a larger voltage level, a bypass signal commands the dual mode low dropout voltage regulator to go into bypass mode and transfer voltage level of the unregulated input voltage source to the output of the dual mode low dropout voltage regulator. The dual mode low dropout voltage regulator provides a smooth transition to the bypass to prevent the output of the dual mode low dropout voltage regulator from decreasing or having a “brown out” until a pass transistor is forced to turn on fully to provide the voltage level of the unregulated input voltage source to fully bypass the low dropout regulating mode of operation.

Abstract: A voltage regulator is described. It comprises an amplification stage to control a voltage level of a first gain node and of a second gain node in response to an input voltage, to activate a first and a second output stage, respectively. It further comprises the first output stage to source a current at an output node of the voltage regulator from a first potential. The voltage regulator comprises the second output stage to sink a current at the output node to a second potential. The voltage regulator comprises a first operating point control circuit to set the voltage level of the first gain node such that a first maintenance current is sourced by the first output stage; and/or a second operating point control circuit to set the voltage level of the second gain node such that a second maintenance current is sunk by the second output stage.

Abstract: Circuits and methods to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit are disclosed as e.g. a LDO or an amplifier. In a preferred embodiment of the disclosure is applied to an LDO. Modification of the resistive voltage divider ratio caused by the feed-forward capacitor during start-up is prevented while the voltage level of a voltage access point of the voltage divider on the feed-forward capacitor is maintained. A start-up circuit comprises a start-up capacitor and a start-up comparator.

Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.

Abstract: Multi-stage amplifiers which provide a constant output voltage subject to load transients are presented. The amplifier has a pass device to source a load current at an output voltage. The amplifier has a first driver circuit to control the pass device based on a reference voltage and based on a first feedback voltage. The amplifier has a sink transistor to sink a first current from the output node to a low potential. Furthermore, the amplifier comprises a bypass transistor configured to couple a sense voltage, to sink a second current from the output node to the low potential. There is a second driver circuit to control the sink transistor and the bypass transistor, based on the reference voltage and based on a second feedback voltage. A voltage divider derives the first feedback voltage, the second feedback voltage and the sense voltage from the output voltage.

Abstract: An overshoot reduction circuit within a low dropout voltage regulator eliminates an overshoot at an output terminal resulting from a transient fault condition occurring at an input or output terminal. The overshoot reduction circuit monitors to sense if there is a transient fault condition occurring at the input or output terminal and provides a Miller capacitance at the output terminal of a differential amplifier of the low dropout voltage regulator to prevent the output of the differential amplifier from being discharged to ground during the transient. A control loop circuit balances current within an active load of the differential amplifier to clamp the output of the differential amplifier to its normal operating point. When the transient fault condition ends, the output voltage of the differential amplifier is set such that a pass transistor of the low dropout regulator responds quickly to resume the regulation to reduce or eliminate the overshoot.

Abstract: Multi-stage amplifiers, such as linear regulators, configured to provide a constant output voltage subject to load transients, are described. The multi-stage amplifier includes a first amplification stage which activates or deactivates a first output stage in response to an input voltage at an input node. The first output stage is configured to source a current at an output node of the multi-stage amplifier from a high potential, when activated. Furthermore, the multi-stage amplifier comprises a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage at the input node. The second output stage is configured to sink a current at the output node of the multi-stage amplifier to a low potential, when activated. The first amplification stage and the second amplification stage are configured to activate the first output stage and the second output stage in a mutually exclusive manner.

Abstract: The present document relates to multi-stage amplifiers, such as linear regulators (e.g. low-dropout regulators). A method and a circuit for reducing leakage current of such multi-stage amplifiers is presented. A voltage regulator is described. The voltage regulator comprises a pass device configured to provide a load current at a regulated output voltage to an output node of the voltage regulator. A source of the pass device is coupled to a first potential of the voltage regulator. Furthermore, the voltage regulator comprises drive circuitry configured to control the pass device via a gate of the pass device, based on a reference voltage and based on a feedback voltage derived from the output voltage. In addition, the voltage regulator comprises leakage reduction circuitry configured to pull-up the gate of the pass device using a second potential; wherein the second potential is higher than the first potential.

Abstract: The present document relates to amplifiers, notably multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. An amplifier comprising an output stage for providing an output current at an output voltage, in dependence of an input voltage at a stage input node of the output stage, is described. The output stage comprises a first input transistor; wherein a gate of the first input transistor is coupled to the stage input node of the output stage. Furthermore, the output stage comprises a first diode transistor; wherein the first diode transistor is arranged in series with the input transistor. In addition, the output stage comprises a pass device configured to provide the output current at the output voltage; wherein the first diode transistor and the pass device form a current mirror.

Abstract: Circuits and methods to improve dynamic load transient performance of circuits supplying high current and having parasitic resistances are disclosed. These circuits comprise e.g. LDOs, amplifiers or buffers. The circuits and methods are characterized by including parasitic resistances, caused by bond wires, metallization of pass devices, and substrate routings, in a loop for fast transient response. Furthermore the circuits comprise a stabilization circuit within said loop and a separate pad for said loop.

Abstract: Multi-stage amplifiers, such as linear regulators, configured to provide a constant output voltage subject to load transients, are described. The multi-stage amplifier comprises a first amplification stage which activates or deactivates a first output stage in response to an input voltage at an input node. The first output stage is configured to source a current at an output node of the multi-stage amplifier from a high potential, when activated. Furthermore, the multi-stage amplifier comprises a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage at the input node. The second output stage is configured to sink a current at the output node of the multi-stage amplifier to a low potential, when activated. The first amplification stage and the second amplification stage are configured to activate the first output stage and the second output stage in a mutually exclusive manner.