Abstract: Multi-stage amplifiers which provide a constant output voltage subject to load transients are presented. The amplifier has a pass device to source a load current at an output voltage. The amplifier has a first driver circuit to control the pass device based on a reference voltage and based on a first feedback voltage. The amplifier has a sink transistor to sink a first current from the output node to a low potential. Furthermore, the amplifier comprises a bypass transistor configured to couple a sense voltage, to sink a second current from the output node to the low potential. There is a second driver circuit to control the sink transistor and the bypass transistor, based on the reference voltage and based on a second feedback voltage. A voltage divider derives the first feedback voltage, the second feedback voltage and the sense voltage from the output voltage.

Abstract: Multi-stage amplifiers, such as linear regulators, configured to provide a constant output voltage subject to load transients, are described. The multi-stage amplifier includes a first amplification stage which activates or deactivates a first output stage in response to an input voltage at an input node. The first output stage is configured to source a current at an output node of the multi-stage amplifier from a high potential, when activated. Furthermore, the multi-stage amplifier includes a second amplification stage configured to activate or to deactivate a second output stage in response to the input voltage at the input node. The second output stage is configured to sink a current at the output node of the multi-stage amplifier to a low potential, when activated. The first amplification stage and the second amplification stage are configured to activate the first output stage and the Second output stage in a mutually exclusive manner.

Abstract: An LDO circuit with a current sink stage reduces significantly overshooting of the output voltage due to sudden changes of output current. The activation of the current sink stage is independent of the overshoot percentage of the regulated output voltage. The disclosure doesn't require large output capacitors to avoid the possibility of brownouts of chips supplied by the LDO.

Abstract: Circuits and methods to maintain a resistive voltage divider ratio during start-up of an electronic circuit comprising a feed-forward capacitor across a feedback resistor using a dynamic start-up circuit are disclosed as e.g. a LDO or an amplifier. In a preferred embodiment of the disclosure is applied to an LDO. Modification of the resistive voltage divider ratio caused by the feed-forward capacitor during start-up is prevented while the voltage level of a voltage access point of the voltage divider on the feed-forward capacitor is maintained. A start-up circuit comprises a start-up capacitor and a start-up comparator.

Abstract: Methods and circuits for linearly controlling a limited, constant current during startup of LDOs, amplifiers, or DC-to-DC converters independent of load capacitor size and controlling a clean transition without glitches from a constant current (CC) mode during startup to a constant voltage (CV) mode during normal operation (CC-CV method) are disclosed. The constant current control loop and the constant voltage control loop are implemented in such a way that at the end of startup the voltage loop has taken over control and the current loop is moved far away from its active transistor region, allowing a switch of modes to occur without any nasty transitions on the output.

Abstract: The present document relates to amplifiers, notably multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. An amplifier comprising an output stage for providing an output current at an output voltage, in dependence of an input voltage at a stage input node of the output stage, is described. The output stage comprises a first input transistor; wherein a gate of the first input transistor is coupled to the stage input node of the output stage. Furthermore, the output stage comprises a first diode transistor; wherein the first diode transistor is arranged in series with the input transistor. In addition, the output stage comprises a pass device configured to provide the output current at the output voltage; wherein the first diode transistor and the pass device form a current mirror.

Abstract: Circuits and methods to control current through a device biasing an output device in case the supply voltage is not higher than the output voltage are disclosed. The circuits and methods are applicable to e.g. LDOs, amplifiers, or buffers. A control loop detects if the supply voltage is not higher than the output voltage and regulates the drain-source voltage of the biasing device. The disclosure reduces power consumption in a driver stage in case the supply voltage is not higher than the output voltage.

Abstract: Circuits and methods to achieve a clean start-up process and power saving of pulsed enabled electronic devices having an output capacitor and components requiring biasing during normal operating conditions are disclosed. These electronic devices could be e.g. LDOs, amplifiers or buffers. A set of switches are enabling bias currents from the output capacitor to internal nodes requiring biasing under normal operational conditions as e.g. output nodes of amplifying means.

Abstract: Methods and circuits for linearly controlling a limited, constant current during startup of LDOs, amplifiers, or DC-to-DC converters independent of load capacitor size and controlling a clean transition without glitches from a constant current (CC) mode during startup to a constant voltage (CV) mode during normal operation (CC-CV method) are disclosed. The constant current control loop and the constant voltage control loop are implemented in such a way that at the end of startup the voltage loop has taken over control and the current loop is moved far away from its active transistor region, allowing a switch of modes to occur without any nasty transitions on the output.

Abstract: Circuits and methods to control current through a device biasing an output device in case the supply voltage is not higher than the output voltage are disclosed. The circuits and methods are applicable to e.g. LDOs, amplifiers, or buffers. A control loop detects if the supply voltage is not higher than the output voltage and regulates the drain-source voltage of the biasing device. The disclosure reduces power consumption in a driver stage in case the supply voltage is not higher than the output voltage.

Abstract: A circuit is provided with inrush current protection through control of the output current at start-up by a current source that does not rely on the output capacitor and which provides a smooth transition from a controlled current mode during a start-up phase to a voltage regulation mode.

Abstract: An apparatus and method for a system with improved power supply rejection ratio (PSRR) over a wide frequency range. The improved PSRR is achieved by negating the influence of the parasitic capacitance associated with the bias lines and the introduction of a regulated power supply with embodiments associated with providing a ripple free and regulated supply. With reduction of parasitic capacitance, and providing an ENABLE switch by a pre-regulated supply, the degradation of the PSRR is achieved. The embodiments include both n-channel and p-channel MOSFETs implementations, and a positive and negative regulated power supply voltage. With the combined influence of the utilization of the VREG supply, and the lowering of battery-to-bias line capacitance using design layout and improved floor planning an improved PSRR over a wide frequency distribution is achieved.

Abstract: An overshoot reduction circuit within a low dropout voltage regulator eliminates an overshoot at an output terminal resulting from a transient fault condition occurring at an input or output terminal. The overshoot reduction circuit monitors to sense if there is a transient fault condition occurring at the input or output terminal and provides a Miller capacitance at the output terminal of a differential amplifier of the low dropout voltage regulator to prevent the output of the differential amplifier from being discharged to ground during the transient. A control loop circuit balances current within an active load of the differential amplifier to clamp the output of the differential amplifier to its normal operating point. When the transient fault condition ends, the output voltage of the differential amplifier is set such that a pass transistor of the low dropout regulator responds quickly to resume the regulation to reduce or eliminate the overshoot.

Abstract: A dual mode low dropout voltage regulator has a low dropout regulation mode and a bypass mode and provides a smooth transition between mode transitions taking place under load. When an accessory requires a larger voltage level, a bypass signal commands the dual mode low dropout voltage regulator to go into bypass mode and transfer voltage level of the unregulated input voltage source to the output of the dual mode low dropout voltage regulator. The dual mode low dropout voltage regulator provides a smooth transition to the bypass to prevent the output of the dual mode low dropout voltage regulator from decreasing or having a “brown out” until a pass transistor is forced to turn on fully to provide the voltage level of the unregulated input voltage source to fully bypass the low dropout regulating mode of operation.

Abstract: A pass device configured from a common gate transistor, wherein an input voltage is applied to the source and an output at the drain is applied to a load. The input resistance of the pass device increases as the input voltage is reduced and limits the useful range of the input voltage. Increasing the gate to source voltage (Vgs) by applying a negative voltage to the gate reduces the input resistance and increases the range of operation of the pass device.

Abstract: A pass device configured from a common gate transistor, wherein an input voltage is applied to the source and an output at the drain is applied to a load. The input resistance of the pass device increases as the input voltage is reduced and limits the useful range of the input voltage. Increasing the gate to source voltage (Vgs) by applying a negative voltage to the gate reduces the input resistance and increases the range of operation of the pass device.

Abstract: Circuits and methods to reduce the size of output capacitors of LDOs or amplifiers are disclosed. Nonlinear mirroring of the load current allows scaling of gain or adapting small signal impedance of a pass transistor depending on other inputs, in case of a preferred embodiment, allows to reduce small signal impedance at the gate of the pass transistor as the load current increases, hence allowing to reduce the size of an output capacitor without compromising stability of the system.

Abstract: A low dropout (LDO) regulator with a limited startup inrush current is disclosed. The LDO includes a power source, error amplifier, pass transistor, feedback network, and a current limit control whose input is electrically connected to the pass transistor and the electrical output of the error amplifier and whose output limits current during startup. The LDO can include a current control limit comparator including a power source, and output of the pass transistor. The LDO can also include a bypass mode current control limit comparator having a first input voltage of the error amplifier, and a second input voltage from the error amplifier.

Abstract: The present document relates to a pre-charge circuit of electronic circuits having Miller compensation and significant output capacitance such as LDOs or multistage amplifiers. The pre-charge circuit limits an inrush current right after enabling of the electronic circuit. The pre-charge circuit limits and clamps the fast charging of the Miller capacitor. A delay circuit disables the pre-charge circuit when the bias conditions of the Miller capacitor are close to normal bias conditions.

Abstract: Circuits and methods to control current through a device biasing an output device in case the supply voltage is not higher than the output voltage are disclosed. The circuits and methods are applicable to e.g. LDOs, amplifiers, or buffers. A control loop detects if the supply voltage is not higher than the output voltage and regulates the drain-source voltage of the biasing device. The disclosure reduces power consumption in a driver stage in case the supply voltage is not higher than the output voltage.