Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.

Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.

Abstract: A method for manufacturing a semiconductor device includes forming a first fin structure and a second fin structure, wherein an isolation region is located between the fin structures, and wherein a space is located between the fin structures and above the isolation region; depositing a blocking layer over the first fin structure, the isolation region, and the second fin structure, wherein an upper portion of the blocking layer is located above the first fin structure and the second fin structure, and wherein a lower portion of the blocking layer fills the space located between the first fin structure and the second fin structure; removing the upper portion of the blocking layer; and while the lower portion of the blocking layer remains over the isolation region, performing an etch process to recess the first fin structure and the second fin structure.

Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

Abstract: An optical photographing lens assembly includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements of the optical photographing lens assembly has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the first lens element is concave in a paraxial region thereof. The object-side surface of the first lens element is aspheric and has at least one critical point in an off-axis region thereof.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

Abstract: Disclosed herein is a dual-active bridge converter and methods of operating the same. The dual-active bridge converter can include a transformer, a DC-AC converter, an AC-DC converter, and/or a control device. The DC-AC converter can be coupled to a first DC bus and a primary side of the transformer. The AC-DC converter can be coupled to a secondary side of the transformer and a second DC bus. The control device can send a first PWM signal to the DC-AC converter and a second PWM signal to the AC-DC converter. The first and second PWM signals can initiate the output voltage at zero, add jump edges at odd-numbered current harmonics, or make a phase of the input voltage trail a phase of the output voltage of the DC-AC converter. The control device can adjust the PWM signals for transformer current regulation or pulse overlap control.

Abstract: A biological particle enrichment apparatus and a pico-droplet generator thereof are provided. The pico-droplet generator includes a container, a hollow needle connected to the container, a first piezoelectric member disposed on the container, and a second piezoelectric member disposed on the hollow needle. The container can receive a liquid specimen having biological particles. The hollow needle and the container are fluid communicated with each other, and an inner diameter of the container is within a range from 5 times to 30 times of an inner diameter of the hollow needle. The first piezoelectric member is annularly disposed on a surrounding lateral side of the container, and enables the biological particles in the container to move along a direction away from the surrounding lateral side by vibrating the container. The second piezoelectric member can squeeze the hollow needle, so that the liquid specimen flows outwardly to form a pico-droplet.

Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: A controlling method for a wireless communication device is provided. The controlling method for the wireless communication device includes: attaching a first Universal Subscriber Identity Module (USIM) to a Long-Term Evolution (LTE) network; determining whether a second USIM is camped on the LTE network; detecting whether a paging collision is happened, if the second USIM is camped on the LTE network; generating a requested International Mobile Subscriber Identity (IMSI) offset for the second USIM, if the paging collision is happened, wherein the requested IMSI offset is 1 or min(T, nB)?1, T is a default paging period and nB is a number of paging occurrences within the default paging period; transmitting an attach request with the requested IMSI offset to the LTE network for the second USIM; receiving a negotiated IMSI offset from the LTE network; and attaching the second USIM to the LTE network with the negotiated IMSI offset.

Abstract: A power measurement circuit, a chip and a communication terminal. The power measurement circuit comprises a power measurement unit (100), a reference current generation unit (200), a voltage-current conversion unit (300) and an operation output unit (400), wherein an output end of the power measurement unit (100) is connected to an input end of the voltage-current conversion unit (300), and an output end of the voltage-current conversion unit (300) and an output end of the reference current generation unit (200) are respectively connected to an input end of the operation output unit (400). By means of the circuit, during the process of a power measurement unit (100) converting, into a direct-current voltage, a received radio frequency signal to be measured, sensitivity adjustment is performed, such that the measurement sensitivity can be effectively adjusted.

Abstract: A power supply suppression circuit (10), a chip and a communication terminal that only achieve the enhancement of the power supply suppression capability from an AC, without generating additional circuit power consumption. The power supply suppression circuit (10) comprises a sampling unit (105), a compensation unit (106), and an amplification unit (107). The sampling unit (105) is connected to the compensation unit (106), and the compensation unit (106) is connected to the amplification unit (107). The power supply suppression circuit (10) obtains an AC signal from a preset sampling node position of a low dropout regulator, and generates an enhancement signal in phase with the AC signal on a power supply (Vdd) on the basis of the AC signal, such that the input end voltage of the power output stage of the low dropout regulator immediately follows the voltage change of the power supply (Vdd).

Abstract: Aspects of the present disclosure provide an automated labeling system. For example, the automated labeling system can include an automated labeling module (ALM) configured to receive wireless signals and ground truth of learning object and label the wireless signals with the ground truth when receiving the ground truth to generate labeled training data. The automated labeling system can also include a training database coupled to the ALM. The training database can be configured to store the labeled training data.

Abstract: The present disclosure generally relates to underwater user interfaces.

Abstract: An adaptive overshoot-voltage suppression circuit (100), a reference circuit, a chip and a communication terminal. The adaptive overshoot-voltage suppression circuit (100) comprises an overshoot-voltage suppression unit (1001) and a voltage-current conversion unit (1002), wherein an input end of the overshoot-voltage suppression unit (1001) is connected to a preset sampling point on a reference circuit to be tested, an output end of the overshoot-voltage suppression unit (1001) is connected to an input end of the voltage-current conversion unit (1002), and an output end of the voltage-current conversion unit (1002) is connected to a preset adjustment point on said reference circuit.

Abstract: Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.