Patents by Inventor An-Cheng Chou

An-Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230065104
    Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 2, 2023
    Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng
  • Publication number: 20230063758
    Abstract: A semiconductor device includes a memory circuit, an error correction code circuit, a register circuit and a write circuit. The memory circuit is configured to output, in response to at least one address signal, first data associated with at least one memory cell in the memory circuit. The error correction code circuit is configured to convert the first data to second data and configured to generate error information when the first data is not identical to the second data. The register circuit is configured to output, based on the error information, reset information corresponding to the at least one address signal. The write circuit is configured to reset the at least one memory cell according to the reset information. A method is also disclosed herein.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zheng-Jun LIN, Pei-Ling TSENG, Hsueh-Chih YANG, Chung-Cheng CHOU, Yu-Der CHIH
  • Publication number: 20230067300
    Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Publication number: 20230068714
    Abstract: A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Chou, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11587875
    Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: U-Ting Chiu, Yu-Shih Wang, Chun-Cheng Chou, Yu-Fang Huang, Chun-Neng Lin, Ming-Hsi Yeh
  • Patent number: 11571825
    Abstract: A utility knife is provided, including: a housing, defining an operation compartment and a storage compartment; a blade holder, movably received within the operation compartment; a blade storing carrier, movably received within the storage compartment, including a receiving portion for receiving at least one spare blade and a grip portion; and a locking mechanism, including a base body, a movable member, a first engaging member and a second engaging member, the base body being disposed to the housing, the movable member being attached to the base body and movable between a locking position and a release position, the first engaging member being disposed on and movable with the movable member, the first engaging member and the second engaging member are releasably engaged with each other so that the blade storing carrier is detachable from the housing.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: February 7, 2023
    Assignees: MING SHIN TOOLS CO., LTD.
    Inventors: Yung-Shun Chen, Cheng-Chou Wu
  • Patent number: 11569749
    Abstract: A wide input voltage range power converter circuit in a one-stage-two-switch configuration has a power input terminal, a switch node connected to the power input terminal, a transformer, two electronic switches, a pulse width modulation (PWM) circuit, and an output circuit. An input side of the transformer has a first winding and a second winding that are connected to the switch node. An output side of the transformer has an output winding. A turns ratio between the first winding and the output winding is different from a turns ratio between the second winding and the output winding. The two electronic switches are respectively connected to the first winding and the second winding in series. The PWM circuit is connected to the power input terminal and control terminals of the two electronic switches. The output circuit is connected to the output winding.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: January 31, 2023
    Assignee: MINMAX TECHNOLOGY CO., LTD.
    Inventors: Cheng-Chou Wu, Chien-Ming Chen
  • Patent number: 11557344
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
  • Patent number: 11551979
    Abstract: A method for manufacturing a semiconductor structure includes etching trenches in a semiconductor substrate to form a semiconductor fin between the trenches; converting sidewalls of the semiconductor fin into hydrogen-terminated surfaces each having silicon-to-hydrogen (S—H) bonds; after converting the sidewalls of the semiconductor fin into the hydrogen-terminated surfaces, depositing a dielectric material overfilling the trenches; and etching back the dielectric material to fall below a top surface of the semiconductor fin.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Cheng Chou, Shiu-Ko Jangjian, Cheng-Ta Wu
  • Patent number: 11551590
    Abstract: A display apparatus configured to receive a command, and convert the command to displayable information to an outside pedestrian or drivers in other vehicles may include a main body that includes a securing portion to secure the display apparatus to a vehicle; a communication unit to receive the command; a processor to convert the command to displayable information; a display portion having a displaying layer to display information; and a power managing unit to store and provide electrical energy for the display apparatus. In one embodiment, the power managing unit may include a power generating unit to be positioned to overlap with the displaying layer.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: January 10, 2023
    Inventors: Wei Cheng Chou, Chih-Hao Liu
  • Patent number: 11545215
    Abstract: A method for writing to a memory is disclosed. The method includes generating a write current that flows to a memory cell of the memory, generating a mirror current that mirrors the write current, and inhibiting application of a write voltage to the memory cell of the memory based on the mirror current. A device that performs the method is also disclosed. A memory that includes the device is also disclosed.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chung-Cheng Chou
  • Patent number: 11545885
    Abstract: An auxiliary power supply circuit operating within a wide input voltage range has a voltage follower unit and a voltage comparison unit. The voltage follower unit has an electronic switch, a resistor, and a Zener diode. The electronic switch has a first terminal electrically connected to a voltage input terminal of the working voltage conversion circuit, a second terminal electrically connected to a voltage output terminal of the working voltage conversion circuit, and a control terminal. The resistor is electrically connected between the first terminal and the control terminal of the electronic switch. The Zener diode has a cathode electrically connected to the control terminal of the electronic switch. The voltage comparison unit has a detecting terminal electrically connected to the voltage input terminal of the working voltage conversion circuit, and an output terminal electrically connected to the control terminal of the electronic switch.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: January 3, 2023
    Assignee: MINMAX TECHNOLOGY CO., LTD.
    Inventor: Cheng-Chou Wu
  • Publication number: 20220411421
    Abstract: 4-Amino-imidazoquinoline compounds and use thereof are disclosed. The compounds of the invention are Toll-like receptor 7 (TLR7) and TLR8 dual agonists, which exhibit activities in inducing IL-12 and IP-10 expression without over-inducing IL-6. The TLR 7/8 dual agonists are potentially useful medications as immune response modifiers. Use of a compound or salt thereof according to the invention in the manufacture of a medicament for treating a disease or a condition wherein activation of TLR7 and/or TLR8 provides a benefit in a subject in need thereof is disclosed. A compound or a pharmaceutical composition for use in treating a viral infection, cancer, and/or an allergic disease, or for use in activating immune responses that are effective against a viral infection, a tumor, and/or an allergic disease in a subject in need thereof is also disclosed.
    Type: Application
    Filed: October 20, 2020
    Publication date: December 29, 2022
    Inventor: Yu-Cheng CHOU
  • Publication number: 20220406647
    Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.
    Type: Application
    Filed: September 21, 2021
    Publication date: December 22, 2022
    Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Publication number: 20220401956
    Abstract: A drug screening platform simulating hyperthermic intraperitoneal chemotherapy including a dielectrophoresis system, a microfluidic chip and a heating system is disclosed. The dielectrophoresis system is used to provide a dielectrophoresis force. The microfluidic chip includes a cell culture array and observation module and a drug mixing module. The cell culture array and observation module are used to arrange the cells into a three-dimensional structure through the dielectrophoresis force to construct a three-dimensional tumor microenvironment. The drug mixing module is coupled to the cell culture array and observation module and used to automatically split and mix the inputted drugs and output the drug combinations into the cell culture array and observation module.
    Type: Application
    Filed: August 5, 2021
    Publication date: December 22, 2022
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Te-Yu CHAO, Yu-Ching TUNG, Mao-Chih HSIEH, Yu-Ting TAI, Bing-Ying HO, Wei-Chia CHANG, Sung-Yang WEI, Chang-Hung HSIEH, Chung-Cheng CHOU, Jen-Tsan CHI, Long HSU, Hwan-You CHANG, Huang-Ming Philip CHEN, Cheng-Hsien LIU
  • Patent number: 11527285
    Abstract: A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Zheng-Jun Lin, Pei-Ling Tseng
  • Publication number: 20220376079
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
  • Publication number: 20220366980
    Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Chung-Cheng Chou, Tien-Yen Wang
  • Publication number: 20220364995
    Abstract: A portable ring-type fluorescence optical system for observing microfluidic channel and an operating method thereof are disclosed. The portable ring-type fluorescence optical system includes a photographic chip, a first polarizer, an objective lens, a ring-type fluorescent light source, a biological sample on a microfluidic chip, a second polarizer and a bottom illumination light source arranged in order from top to bottom. The ring-type fluorescent light source is used to generate a ring-type fluorescent light to the biological sample on the microfluidic chip. The objective lens is used to magnify a fluorescent image of the biological sample on the microfluidic chip to focus on the photographic chip. The first polarizer disposed under the photographic chip and the second polarizer disposed under the biological sample form a non-zero angle to each other to block reflected lights that the biological sample reflects the lights emitted by the bottom illumination light source.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 17, 2022
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Sung-Yang WEI, Long HSU, Hwan-You CHANG, Huang-Ming CHEN, Jen-Tsan CHI, Chung-Cheng CHOU, Yuh-Cherng LAI, Hung-Yu YEH, Ting-Chou WEI, Yun-Ting YAO, Cheng-Hsien LIU
  • Publication number: 20220366602
    Abstract: The disclosure discloses an object positioning method and system. The object positioning method includes: acquiring an original object image including a to-be-positioned object; demagnifying the original object image; inputting a demagnified object image to a rough-positioning model for identification, to determine a plurality of rough feature positions; acquiring a plurality of image blocks from the original object image according to the rough feature positions; inputting the image blocks to a precise-positioning model for identification, to determine a plurality of precise feature positions; and determining a position of the to-be-positioned object in the original object image.
    Type: Application
    Filed: March 22, 2022
    Publication date: November 17, 2022
    Inventors: CHENG-CHOU CHEN, CHIA-CHING LIAO, AN-CHU HSIAO