Abstract: A method includes forming a carbon-containing layer with a carbon atomic percentage greater than about 25 percent over a first hard mask layer, forming a capping layer over the carbon-containing layer, forming a first photo resist over the capping layer, and etching the capping layer and the carbon-containing layer using the first photo resist as a first etching mask. The first photo resist is then removed. A second photo resist is formed over the capping layer. The capping layer and the carbon-containing layer are etched using the second photo resist as a second etching mask. The second photo resist is removed. A third photo resist under the carbon-containing layer is etched using the carbon-containing layer as etching mask. A dielectric layer underlying the third photo resist is etched to form via openings using the third photo resist as etching mask. The via openings are filled with a conductive material.

Abstract: An infrared control device is configured for use in a mesh network environment to control a controlled device by transmitting an infrared signal. The controlled device includes an identification tag. The identification tag includes a first control instruction. The control device includes a tag identification module and a database. The tag identification module scans the identification tag to identify the first control instruction. The database is electrically connected to the tag identification module to store the first control instruction.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.

Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

Abstract: A ratchet wrench is provided, including: a main body and a handling assembly. The main body includes a head portion being assembled with a ratchet head and a handling portion remote from the head portion. The handling assembly includes a casing coveringly disposed on the handling portion, and the casing defines a receiving space which is configured to receive at least one object and has at least one opening disposed therethrough. Part of an outer surface of the handling portion is flush with or protrusive beyond the at least one opening, and a material of the handling portion is different from a material of the casing.

Abstract: A wide input voltage range power converter circuit in a one-stage-two-switch configuration has a power input terminal, a switch node connected to the power input terminal, a transformer, two electronic switches, a pulse width modulation (PWM) circuit, and an output circuit. An input side of the transformer has a first winding and a second winding that are connected to the switch node. An output side of the transformer has an output winding. A turns ratio between the first winding and the output winding is different from a turns ratio between the second winding and the output winding. The two electronic switches are respectively connected to the first winding and the second winding in series. The PWM circuit is connected to the power input terminal and control terminals of the two electronic switches. The output circuit is connected to the output winding.

Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

Abstract: An anti-PD-L1 antibody, or an antigen-binding fragment thereof, comprising: a heavy chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 2-4, 6-8, 10-12, 14-16, or 18-20; and/or a light chain variable region comprising the three CDRs with the sequences of SEQ ID NOs: 22-24, 26-28, 30-32, 34-36, or 38-40, wherein the antibody is a chimeric, humanized, composite, or human antibody.

Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.

Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.

Abstract: The present teaching is generally directed to soft magnetic alloys. In particular, the present teaching is directed to soft magnetic alloys including Samarium (“Sm”). In a non-limiting embodiment, an Sm-containing magnetic alloy is described including 15 wt % to 55 wt % of Cobalt (“Co”), less than 2.5 wt % of Sm, and 35 wt % to 75 wt % of Iron (“Fe”). The Sm-containing magnetic alloy may further include at least one element X, selected from a group including Vanadium (“V”), Boron (“B”), Carbon (“C”), Chromium (“Cr”), Manganese (“Mn”), Molybdenum (“Mo”), Niobium (“Nb”), Nickel (“Ni”), Titanium (“Ti”), Tungsten (“W”), and Silicon (“Si”). The Sm-containing magnetic alloy may further have a magnetic flux density of at least 2.5 Tesla.

Abstract: A fan module and an electronic device are provided. The fan module includes a hub and a plurality of blades. The blades are mounted around the hub, and each of the blades has a first end that is connected to a periphery of the hub and a second end that is relatively away from the hub. A first axial direction distance in the axial direction is provided between a first point of the first end that is relatively away from the top surface and the top surface. A second axial direction distance in the axial direction is provided between a second point of the first end that is near the top surface and the top surface. A ratio of the second axial direction distance to the first axial direction distance is 0.4 to 0.5.

Abstract: Methods for forming a magneto-resistive memory device and a capacitor in an interconnect structure are disclosed herein. An exemplary method includes forming a first level interconnect metal layer and a second level interconnect metal layer of an interconnect structure. The method further includes simultaneously forming a first plurality of layers in a first region of the interconnect structure and a second plurality of layers in a second region of the interconnect structure, wherein the first plurality of layers and the second plurality of layers are disposed between the first level interconnect metal layer and the second level interconnect metal layer. The first plurality of layers is configured as a magneto-resistive memory device. The second plurality of layers is configured as the capacitor. The magneto-resistive memory device and the capacitor are each coupled to the first level interconnect metal layer and the second level interconnect metal layer.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: A circuit includes a bias voltage generator and a current limiter. The bias voltage generator is configured to receive a first reference voltage and output a bias voltage responsive to a first current and the first reference voltage. The current limiter is configured to receive a second current at an input terminal, a second reference voltage, and the bias voltage, and, responsive to the second reference voltage and a voltage level of the input terminal, limit the second current to a current limit level, the voltage level of the input terminal being based on the bias voltage.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: A computing device obtains multimedia content relating to a user of the computing device and generates a user interface. In a first mode of operation, the user interface displays a plurality of graphical thumbnails each depicting a cosmetic result, each graphical thumbnail corresponding to a cosmetic template, each of the plurality of cosmetic templates comprising a listing of cosmetic effects utilized for achieving each corresponding cosmetic result. A selection is obtained from the user of one or more graphical thumbnails to select one or more cosmetic templates. Responsive to operating in the second mode of operation, a corresponding listing of cosmetic effects is displayed for each of the one or more selected cosmetic templates and obtaining selection of one or more of the displayed cosmetic effects.