Abstract: The present disclosure provides a dog nose print recognition method and system. The dog nose print recognition method includes: collecting a nose image of a dog, acquiring the nose image, and processing the nose image to obtain a plurality of regional images to be recognized; performing key point detection on the plurality of regional images to be recognized to obtain key points corresponding to the regional images to be recognized, and using the key points to perform alignment processing of the regional images to be recognized to obtain aligned regional images to be recognized; and performing dog nose print feature vector extraction and recognition on the aligned regional images to be recognized, and determining a dog identity recognition result through the dog nose print feature vector extraction and recognition. The system includes modules corresponding to the steps of the method.

Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.

Abstract: The present disclosure provides a method and system for optimizing first-diffraction-order reconstruction of holograms, a device and a medium, and relates to the field of image processing. The method includes: acquiring a target image; determining a target image light field according to the target image; calculating a target diffraction field for the target image light field by performing backward propagation by a set distance; constructing a U-Net network model; and inputting the target diffraction field into a trained U-Net network model to acquire an optimized hologram. The trained U-Net network model is obtained by constructing a U-Net network model and training and optimizing the U-Net network model, thereby continuously improving the quality of the zero-diffraction-order reconstructed image of the initial hologram and finally achieving the effect of optimizing the first-diffraction-order reconstructed image of the hologram.

Abstract: The present disclosure provides a semiconductor package structure, relating to the technical field of semiconductors. The semiconductor package structure includes: a substrate; and at least one chip stack structure provided on the substrate, where the at least one chip stack structures include a plurality of first chips vertically stacked, each of the first chips includes a first conductive plug set, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure.

Abstract: A radiation therapy system may include a magnetic resonance imaging (MRI) device configured to acquire MRI data with respect to a region of interest (ROI). The MRI device may include a main magnet that is around a longitudinal axis and configured to generate a magnetic field. The MRI device may also include a radiation therapy device configured to perform a treatment on at least one portion of the ROI by delivering, based on the MRI data, therapeutic radiation to the at least one portion of the ROI. The radiation therapy device may be rotatable around the longitudinal axis. The MRI device may also include a first shielding structure configured to provide interference shielding for the MRI device or the radiation therapy device. The radiation therapy device may be rotatable relative to the first shielding structure around the longitudinal axis.

Abstract: Embodiments of the disclosure provide a method and apparatus for running a service, and an electronic device. An embodiment of the method includes: determining a target deployment manner of a graphics processing unit (GPU) according to performance data of each service in a service set, where the deployment manner includes: dividing the GPU into sub-GPUs of a respective size and determining a service configured to be run by each sub-GPU; and switching, for the service in the service set, running of the service from a sub-GPU indicated by a current deployment manner to a sub-GPU indicated by the target deployment manner. According to the embodiment, waste of the GPU can be reduced by running a plurality of services on the GPU.

Abstract: Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.

Abstract: An identity certificate may be issued to a blockchain node. The issuance may include issuing a first identity certificate to a first terminal and receiving a second identity certificate issuance request that is from the first terminal. A second identity certificate may be issued to the first terminal, and a third identity certificate issuance request is received from the second terminal. A third identity certificate is issued to the second terminal, so that the second terminal forwards the third identity certificate to the third terminal.

Abstract: An access point (AP) and a station (STA) communicate with each other, with the AP indicating to the STA either or both of a preamble detection (PD) channel and a signaling (SIG) content channel and with the STA being initially monitoring a primary frequency segment of a plurality of frequency segments in an operating bandwidth of the AP. A downlink (DL) or triggered uplink (UL) communication is performed between the AP and the STA during a transmission opportunity (TXOP) such that: (i) during the TXOP, the STA monitors a preamble on the PD channel and decodes a SIG content on the SIG content channel; and (ii) after an end of the TXOP, the STA switches to the primary frequency segment.

Abstract: It relates to zirconia particles containing molybdenum and each having a polyhedron shape. The molybdenum is preferably unevenly distributed in surface layers of the zirconia particles. It also relates to a method for producing the zirconia particles. The method includes mixing a zirconium compound and a molybdenum compound to form a mixture and firing the mixture.

Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.

Abstract: This disclosure provides a device identity authentication method and apparatus, an electronic device, and a computer-readable medium. The device identity authentication method includes generating, by a terminal device, a first identity authentication message in response to an identity authentication instruction; sending the first identity authentication message to the second device for the second device to authenticate an identity of the terminal device based on the first identity authentication message to obtain a first identity authentication result; receiving, by the terminal device, a second identity authentication message; wherein the second identity authentication message is a message sent by the second device when the first identity authentication result is passed; authenticating an identity of the second device based on the second identity authentication message to obtain a second identity authentication result.

Abstract: Niobium oxide particles which have a controlled crystal shape and exhibit excellent characteristics are provided. The niobium oxide particles include molybdenum. The niobium oxide particles preferably have a polyhedral, columnar or acicular shape. The MoO3 content (M1) measured by XRF analysis of the niobium oxide particles is preferably 0.1 to 40 mass % relative to the niobium oxide particles taken as 100 mass %. A method for producing the niobium oxide particles described above includes calcining a niobium compound in the presence of a molybdenum compound.

Abstract: A seismic quantitative prediction method for shale total organic carbon (TOC) based on sensitive parameter volumes is as follows. A target stratum for a TOC content to be measured is determined, logging curves with high correlations with TOC contents are analyzed, the logging curves are found as sensitive parameters; sample data are constructed using the sensitive parameters; a radial basis function (RBF) neural network is trained with the sample data as an input and the TOC content at a depth corresponding to the sample data as an output to obtain a RBF neural network prediction model; sensitive parameter volumes are obtained by using the sensitive parameters and post stack three-dimension seismic data to invert; prediction samples are constructed using the sensitive parameter volumes; the predicted samples are input to the RBF neural network prediction model to calculate corresponding TOC values, thereby the TOC content of the target stratum is predicted.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: A semiconductor structures and a method for forming the same are provided. The semiconductor structure includes first nanostructures and second nanostructures spaced apart from the first nanostructures in a first direction. A left-most point of the first nanostructures and a left-most point of the second nanostructures has a first distance in the first direction. The semiconductor structure further includes first source/drain features attached to opposite sides of the first nanostructures in a second direction being orthogonal to the first direction and third nanostructures and fourth nanostructures spaced apart from the third nanostructures in the first direction. A left-most point of the third nanostructures and a left-most point of the fourth nanostructures has a second distance in the first direction. In addition, the third nanostructures are wider than the first nanostructures in the first direction, and the first distance is smaller than the second distance.

Abstract: A method for preparing antibacterial stainless steel by surface alloying includes the steps of coating an infiltration promoter layer on a stainless steel surface, coating an antibacterial metal layer on a surface of the infiltration promoter layer, and performing heat treatment of the stainless steel to diffuse an antibacterial metal into the stainless steel. This method can be applied to various types of stainless steel, and the antibacterial metal can be diffused and quenched into the stainless steel, such that the finally formed surface of the stainless steel has an antibacterial alloy layer with a specific thickness to provide better corrosion resistance and antibacterial ability without changing the advantages and properties of the antibacterial metal or stainless steel substrate, and the thickness and concentration of the antibacterial metal layer, and the parameters for heat treatment can be adjusted to control the chemical composition and thickness of the antibacterial alloy layer.

Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.

Abstract: A gate structure includes a metal layer, a barrier layer, and a work function layer. The barrier layer covers a bottom surface and sidewalls of the metal layer. The barrier layer includes fluorine and silicon, or fluorine and aluminum. The barrier layer is a tri-layered structure. The work function layer surrounds the barrier layer.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.