Patents by Inventor An-Cheng Liu

An-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240084135
    Abstract: A resin composition and uses thereof are provided. The resin composition includes: (A) an epoxy resin; (B) a bismaleimide resin; and (C) a first flame retardant having a structure of formula (I): Wherein Ar is a C3 to C18 heteroaryl or a C6 to C18 aryl; R1 is H or a C1 to C18 alkyl; and R2 and R3 are independently H, a C1 to C18 alkyl, a C3 to C18 heteroaryl, or a C6 to C18 aryl.
    Type: Application
    Filed: December 7, 2022
    Publication date: March 14, 2024
    Inventors: Tsung-Hsien LIN, Shur-Fen LIU, Pin CHIEN, Kai-Cheng YANG
  • Publication number: 20240087890
    Abstract: A method includes depositing a photoresist layer over a target layer, the photoresist layer comprising an organometallic material; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation; developing the exposed photoresist layer to form a photoresist pattern; forming a spacer on a sidewall of the photoresist pattern; removing the photoresist pattern; after removing the photoresist pattern, patterning the target layer through the spacer.
    Type: Application
    Filed: August 26, 2022
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien HUANG, Chih-Cheng LIU, Tze-Liang LEE
  • Publication number: 20240087947
    Abstract: A semiconductor device and method of manufacture are provided. In some embodiments isolation regions are formed by modifying a dielectric material of a dielectric layer such that a first portion of the dielectric layer is more readily removed by an etching process than a second portion of the dielectric layer. The modifying of the dielectric material facilitates subsequent processing steps that allow for the tuning of a profile of the isolation regions to a desired geometry based on the different material properties of the modified dielectric material.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 14, 2024
    Inventors: Chung-Ting Ko, Yu-Cheng Shiau, Li-Jung Kuo, Sung-En Lin, Kuo-Chin Liu
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20240087932
    Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung TSAI, Ping-Cheng KO, Fang-yu LIU, Jhih-Yuan YANG
  • Publication number: 20240087945
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Tsai-Hao HUNG, Ping-Cheng KO, Tzu-Yang LIN, Fang-Yu LIU, Cheng-Han WU
  • Publication number: 20240086582
    Abstract: Methods for modeling contact pairs in a model of a physical object include generating a contact pair including a contact surface and a target surface, where the contact pair further includes contact elements of the contact surface and the target surface, splitting the contact pair into contact sub-pairs along splitting boundaries, augmenting each contact sub-pair with contact elements from adjacent contact sub-pairs at the splitting boundaries, distributing the augmented contact sub-pairs to a plurality of parallel processors for finite element solutions of the contact sub-pairs, receiving the finite element solutions of the contact sub-pairs from the plurality of parallel processors, and combining the finite element solutions of the contact sub-pairs into finite element solutions of the contact pair.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 14, 2024
    Inventors: Yongyi ZHU, Yong-Cheng Liu, Jeff Beisheim, Grama Bhashyam
  • Publication number: 20240087988
    Abstract: The present disclosure, in some embodiments, relates an integrated chip. The integrated chip includes a substrate. A through-substrate-via (TSV) extends through the substrate. A dielectric liner separates the TSV from the substrate. The dielectric liner is along one or more sidewalls of the substrate. The TSV includes a horizontally extending surface and a protrusion extending outward from the horizontally extending surface. The TSV has a maximum width along the horizontally extending surface.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Hung-Ling Shih, Wei Chuang Wu, Shih Kuang Yang, Hsing-Chih Lin, Jen-Cheng Liu
  • Publication number: 20240088049
    Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a first chip, a second chip, a conductive substrate, a dielectric layer, a vertical conductive structure, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The vias penetrate through the substrate, and a part of the vias is disposed in a first die-bonding region and a second die-bonding region. The electrodes extend from the first board surface to the second board surface through the vias. The dielectric layer is formed on the substrate to cover a lower electrode portion of each of the electrodes. The vertical conductive structure is formed to be partially embedded into the dielectric layer and provide an electrical path between the first and second die-bonding regions. The dam is formed to surround the first and the second die-bonding regions.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: DEI-CHENG LIU, JHIH-WEI LAI
  • Publication number: 20240088559
    Abstract: Embodiments of this application relate to the field of terminal technologies, and provides a millimeter wave module circuit and a terminal device. The first antenna array includes N first antennas, and the second antenna array includes M second antennas, where N is greater than M. The processing module includes a plurality of first processing units. Each of N first antennas is connected to each first processing unit. Each of M second antennas is separately connected to two different first processing units. The first processing unit includes a power amplifier. The processing module is configured to send, through differential feeding, a second signal to the second antenna by using two different first processing units. This can enable a signal coverage of the second antenna array to be increased, improving performance of a millimeter wave module in a coverage region of the second antenna array.
    Type: Application
    Filed: December 22, 2022
    Publication date: March 14, 2024
    Applicant: Honor Device Co., Ltd.
    Inventors: Cheng JIANG, Yu WANG, Zengchao QU, Tianyu PEN, Dongping LIU
  • Publication number: 20240081352
    Abstract: The present disclosure provides a blending method of high-quality and dual-purpose flour for bread and noodles, belonging to the technical field of flour processing. The method includes: selecting flour of a high-quality and dual-purpose wheat variety for bread and noodles as a high-quality basic flour for blending; according to a large gradient experimental design, selecting a gradient range ratio with a sedimentation value ?46.0 mL and a dough development time ?9.6 min, followed by subdividing for small gradient experiments; selecting a ratio with flour sedimentation value and dough development time that reach an ideal value to blend a large amount of flour; and making bread and noodles for scoring, followed by determining a blending ratio if a scoring result reaches an ideal value.
    Type: Application
    Filed: September 11, 2022
    Publication date: March 14, 2024
    Inventors: Yan Zi, Jianmin Song, Xiao Ma, Aifeng Liu, Wei Ju, Haosheng Li, Dungong Cheng, Canguo Wang, Jun Guo, Jianjun Liu, Xinyou Cao, Cheng Liu, Shengnan Zhai, Faji Li, Ran Han, Zhendong Zhao
  • Patent number: 11926340
    Abstract: A distributed centralized automatic driving method comprises a sensor processing module, a perception positioning module, a perception target detection module, a decision-making module, a planning module, and a vehicle control module. By clearly defining data domains and a control process, a modular design is performed to implement each functional method, and each module can be deployed to a control unit of the corresponding data domain according to the load of a computing platform. The distributed centralized automatic driving method has different computing requirements for different scenarios. By means of a distributed design, centralized computing is distributed to different computing unit modules, so as to greatly improve the stability, efficiency and parallelism of the method, thereby improving the overall performance of the method.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: March 12, 2024
    Assignee: AutoCore Technology (Nanjing) Co., Ltd.
    Inventors: Yang Zhang, Cheng Chen, Jie Liu
  • Patent number: 11930632
    Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. According to embodiments of the present disclosure, a height of the work function layer, especially a height of the second portion of the work function layer, is significantly increased, and a height of the first gate material layer is significantly reduced, so that the height ratio of the second portion of the work function layer to the first gate material layer to the second gate material layer is maintained at 3 to 8:1 to 1.5:1; therefore, it can be ensured that the work function of the WL groove filling material layer of the recessed gate structure with a small WL width will be significantly increased, thereby greatly weakening the row hammer effect at the bottom of the WL groove and obviously reducing the GIDL effect at the upper part of the WL groove.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: March 12, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Cheng Liu
  • Patent number: 11929871
    Abstract: The present disclosure provides a method for generating a backbone network, an apparatus for generating a backbone network, a device, and a storage medium. The method includes: acquiring a set of a training image, a set of an inference image, and a set of an initial backbone network; training and inferring, for each initial backbone network in the set of the initial backbone network, the initial backbone network by using the set of the training image and the set of the inference image, to obtain an inference time and an inference accuracy of a trained backbone network in an inference process; determining a basic backbone network based on the inference time and the inference accuracy of the trained backbone network in the inference process; and obtaining a target backbone network based on the basic backbone network and a preset target network.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 12, 2024
    Inventors: Cheng Cui, Tingquan Gao, Shengyu Wei, Yuning Du, Ruoyu Guo, Bin Lu, Ying Zhou, Xueying Lyu, Qiwen Liu, Xiaoguang Hu, Dianhai Yu, Yanjun Ma
  • Patent number: 11929318
    Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Publication number: 20240078653
    Abstract: A visual inspection method of a curved object executed by a visual inspection system. The visual inspection system includes a robotic arm, a camera mounted at a tail end of the robotic arm, a fixing unit mounted under the camera, and a control unit electrically connected to the robotic arm and the camera. Specific steps of the visual inspection method of the curved object are described hereinafter. Fix a curved object which is to be inspected by the fixing unit. Capture the object which is to be inspected with a plurality of groups of preset parameters by the camera. Use the control unit to calculate a better shooting parameter. Use the better shooting parameter by the camera to proceed with visual inspections of the curved objects which are to be inspected in batches.
    Type: Application
    Filed: June 21, 2023
    Publication date: March 7, 2024
    Inventors: SHUN-CHIEN LAN, WEI-CHENG TSENG, CHEN-YI LIU, CHEN-TE CHEN
  • Publication number: 20240076370
    Abstract: The presently disclosed subject matter provides antibodies that bind to GPRC5D and methods of using the same.
    Type: Application
    Filed: December 22, 2022
    Publication date: March 7, 2024
    Applicants: MEMORIAL SLOAN-KETTERING CANCER CENTER, EUREKA THERAPEUTICS, INC.
    Inventors: Renier J. Brentjens, Eric L. Smith, Cheng Liu
  • Publication number: 20240074826
    Abstract: A surgical robot including at least one contact module, a control connection module, at least one first robotic arm, and at least one grip control device. A first transmission member of the control connection module drives the control module through a first transmission connecting member. A first shaft member of the first robotic arm is connected with the first transmission member while the grip control device is connected with the first robotic arm by a transmission interface. A force sensing member of the first robotic arm detects a first reaction force from the contact module so that the first robotic arm sends a feedback control signal to the grip control device to control a grip driving member to generate a force feedback for allowing a grip portion to move. Thereby, users can feel movement of the grip portion caused by the force feedback to avoid accidental iatrogenic injuries.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 7, 2024
    Inventors: PO-YUN LIU, CHUN-HUNG KUO, CHIH-CHENG CHIEN, YEN-CHIEH WANG
  • Publication number: 20240081157
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Application
    Filed: November 6, 2023
    Publication date: March 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11923392
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang