Patents by Inventor An-Chi CHENG

An-Chi CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116090
    Abstract: Provided are a tank support jig and a tank cleaning method. The tank support jig for supporting a cylindrical tank includes a curved body having a first end and a second end that face with an interval in between; and a connecting member disposed across the interval, the connecting member connecting the first end and the second end of the curved body such that the interval is adjustable, in which the curved body and the connecting member form an annular structure for the tank that is to be placed horizontally inside the annular structure with the curved body in close contact with at least part of an outer circumferential face of the tank along a circumferential direction of the tank.
    Type: Application
    Filed: January 28, 2022
    Publication date: April 11, 2024
    Inventors: Chun Cheng Chen, Chi Hsing Fu, Katsuyuki Ebisawa, Bo Yu Lin
  • Publication number: 20240120812
    Abstract: An integrated motor and drive assembly is disclosed and includes a housing, a motor and a drive. The housing includes a motor-accommodation portion and a drive-accommodation portion. The drive includes a power board and a control board. The power board is made of a high thermal conductivity substrate and includes a power element and an encoder disposed on the first side, the first side faces the motor, the power board and the motor are stacked along a first direction, and the second side contacts the housing to from a heat-dissipating route. The control board is disposed adjacent to the power board. The control board and the power board are arranged along a second direction perpendicular to the first direction, and the first direction is parallel to an axial direction of the motor. A part of the power board and a part of the control board are directly contacted to form an electrical connection.
    Type: Application
    Filed: July 17, 2023
    Publication date: April 11, 2024
    Inventors: Chi-Hsiang Kuo, Yi-Yu Lee, Zuo-Ying Wei, Yuan-Kai Liao, Wen-Cheng Hsieh
  • Patent number: 11955379
    Abstract: A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wen Wu, Chun-I Tsai, Chi-Cheng Hung, Jyh-Cherng Sheu, Yu-Sheng Wang, Ming-Hsing Tsai
  • Patent number: 11954779
    Abstract: An animation generation method for tracking a facial expression and a neural network training method thereof are provided. The animation generation method for tracking a facial expression includes: driving a first role model according to an expression parameter set to obtain a virtual expression image corresponding to the expression parameter set; applying a plurality of real facial images to the virtual expression image corresponding to the facial expression respectively to generate a plurality of real expression images; training a tracking neural network according to the expression parameter set and the real expression images; inputting a target facial image to the trained tracking neural network to obtain a predicted expression parameter set; and using the predicted expression parameter set to control a second role model.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: April 9, 2024
    Assignee: DIGITAL DOMAIN ENTERPRISES GROUP LIMITED
    Inventors: Chin-Yu Chien, Yu-Hsien Li, Yi-Chi Cheng
  • Patent number: 11956553
    Abstract: An image sensor device has a first number of first pixels disposed in a substrate and a second number of second pixels disposed in the substrate. The first number is substantially equal to the second number. A light-blocking structure disposed over the first pixels and the second pixels. The light-blocking structure defines a plurality of first openings and second openings through which light can pass. The first openings are disposed over the first pixels. The second openings are disposed over the second pixels. The second openings are smaller than the first openings. A microcontroller is configured to turn on different ones of the second pixels at different points in time.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsin-Chi Chen
  • Patent number: 11955370
    Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Publication number: 20240113164
    Abstract: A process for converting a portion of a dielectric fill material into a hard mask includes a nitrogen treatment or nitrogen plasma to convert a portion of the dielectric fill material into a nitrogen-like layer for serving as a hard mask to form an edge area of a device die by an etching process. After forming the edge area, another dielectric fill material is provided in the edge area. In the completed device, a gate cut area can have a gradient of nitrogen concentration at an upper portion of the gate cut dielectric of the gate cut area.
    Type: Application
    Filed: January 9, 2023
    Publication date: April 4, 2024
    Inventors: Heng-Chia Su, Li-Fong Lin, Zhen-Cheng Wu, Chi On Chui
  • Publication number: 20240112959
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
  • Patent number: 11949050
    Abstract: An LED bulb with a screw base; a cover forming an accommodation space with the screw base; an LED filament located in the accommodation space including a substrate comprising a top surface, a side surface, and an extension direction; a plurality of LED chips disposed on the first top surface; a first electrode arranged on the top surface, electrically connected to the plurality of LED chips; and a first clamp including first and second projecting prongs. The first electrode is clamped by the first and second projecting prongs within the accommodation space. The LED bulb has an imaginary rotational axis not parallel to the extension direction.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: April 2, 2024
    Assignees: EPISTAR CORPORATION, KAISTAR LIGHTING (XIAMEN) CO., LTD.
    Inventors: Tzer-Perng Chen, Tzu-Chi Cheng
  • Patent number: 11948975
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.
    Type: Grant
    Filed: October 24, 2021
    Date of Patent: April 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Publication number: 20240105508
    Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Jitendra Kumar Jha, Justin Mueller, Nazila Haratipour, Gilbert W. Dewey, Chi-Hing Choi, Jack T. Kavalieros, Siddharth Chouksey, Nancy Zelick, Jean-Philippe Turmaud, I-Cheng Tung, Blake Bluestein
  • Publication number: 20240102154
    Abstract: A vacuum processing apparatus (110) for deposition of a material on a substrate is provided. The vacuum processing apparatus (110) includes a vacuum chamber comprising a processing area (111); a deposition apparatus (112) within the processing area (111) of the vacuum chamber; a cooling surface (113) inside the vacuum chamber; and one or more movable shields (220) between the cooling surface (113) and the processing area (111).
    Type: Application
    Filed: February 24, 2020
    Publication date: March 28, 2024
    Inventors: Chun Cheng CHEN, Hung-Wen CHANG, Shin-Hung LIN, Chi-Chang YANG, Christoph MUNDORF, Thomas GEBELE, Jürgen GRILLMAYER
  • Patent number: 11940737
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Patent number: 11942652
    Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 26, 2024
    Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
  • Patent number: 11941298
    Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Chin Chin Cheng, Szu-Chi Liu
  • Patent number: 11942329
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor protruding structure over a substrate and surrounding the semiconductor protruding structure with an insulating layer. The method also includes forming a dielectric layer over the insulating layer. The method further includes partially removing the dielectric layer and insulating layer using a planarization process. As a result, topmost surfaces of the semiconductor protruding structure, the insulating layer, and the dielectric layer are substantially level with each other. In addition, the method includes forming a protective layer to cover the topmost surfaces of the dielectric layer. The method includes recessing the insulating layer after the protective layer is formed such that the semiconductor protruding structure and a portion of the dielectric layer protrude from a top surface of a remaining portion of the insulating layer.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yi Kao, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Patent number: 11942549
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Yu-Cheng Shiau, Chunyao Wang, Chih-Tang Peng, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20240098125
    Abstract: The present disclosure relates to a system, a method and a computer-readable medium for rendering a streaming on a user terminal. The method includes rendering the streaming in a first mode, receiving an environment parameter of the user terminal, receiving a timing when the user terminal closes the streaming, determining a threshold value of the environment parameter based on the timing the user terminal closes the streaming, receiving an updated environment parameter of the user terminal, and rendering the streaming in a second mode if the updated environment parameter meets the threshold value. The second mode includes fewer data objects than the first mode or includes a downgraded version of a data object in the first mode for the rendering. The present disclosure can customize the rendering mode for each user and maximize the satisfaction of viewing streaming for each user.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Yung-Chi HSU, Chung-Chiang HSU, Shao-Yuan WU, Ming-Che CHENG, Ka Chon LOI
  • Publication number: 20240093556
    Abstract: A drill bit for cutting formation comprises a bit body, a plurality of cutters, and a plurality of blades with pockets to accommodate the cutters, respectively. Each of the plurality of cutters has a substrate, an ultra-hard layer, an inclined surface on the top of the ultra-hard layer, wherein the inclined surface slants downward from a cutting edge to a trailing edge. The cutter can improve cutting efficiency and service life.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicants: CNPC USA CORPORATION, BEIJING HUAMEI INC., CHINA NATIONAL PETROLEUM CORPORATION
    Inventors: Jiaqing YU, Chris Cheng, Xu Wang, Ming Yi, Chi Ma