Patents by Inventor An-Chung Chiang
An-Chung Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230183361Abstract: The present disclosure provides compositions and methods for extended release of certain types of antibodies in vivo. It was discovered that such antibodies are able to initiate reversible gelation of hyaluronic acid (HA) by creating a depot that dissociates over time to release the antibody without any impact on its physical and chemical properties as well as its biological activity. As certain tissues and organs, such as eyes, joints and skins, contain HA, local injection of the antibodies to these tissues or organs will result in embedding of the antibody in gel formed from the HA, which becomes a repository of slow-released antibodies. In addition, slow-released formulations can be prepared with antibodies mixed with HA, optionally with other polymers.Type: ApplicationFiled: August 16, 2022Publication date: June 15, 2023Inventors: Laman Alani, Chung-Chiang Hsu, Kirk William Johnson
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Publication number: 20230167958Abstract: A light guide structure with jagged protrusions is configured in a lighting device of a mobile vehicle. The light guide structure comprises a light injecting surface and a light emitting surface. The light injecting surface comprises a middle section and two side sections deployed respectively at opposite ends of the middle section. At least a portion of the side sections has a light guiding area. A light source module forms an irradiation area by the light guide structure, the microstructure of the light guiding area is configured to enable the light from the light guide to pass through the light injecting surface generating refraction, diffusion, or scattering, so as to reduce the generation of stray light, and improve the clarity of the beam contour.Type: ApplicationFiled: May 19, 2022Publication date: June 1, 2023Inventors: CHAO PAI LEE, CHENG CHIH LAI, CHUNG CHIANG PAN
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Patent number: 11661783Abstract: This disclosure is directed to an electric support rod having a driving assembly, an actuating assembly, and a bearing. The driving assembly has a first outer tube and a driving unit in the first outer tube. An internal thread is configured in the first outer tube. The actuating assembly has a second outer tube and a transmission screw rod in the second outer tube. Multiple elastic arms axially are extended from the second outer tube and arranged spacedly around the transmission screw rod. Each elastic arm has an outer thread structure and a hook portion. The second outer tube is inserted in the first outer tube, the internal thread is screwed with the outer thread structure. One end of the transmission screw rod protrudes from the second outer tube to engage the driving unit. The bearing sheathes the transmission screw rod and the hook portion latches the bearing.Type: GrantFiled: March 1, 2022Date of Patent: May 30, 2023Assignees: HSIN CHONG MACHINERY WORKS CO. LTD., FUZHOU MINGFANG AUTOMOBILE PARTS INDUSTRY CO., LTD.Inventors: Chi-Wang Wu, Feng-Lin Yang, Jeffrey Chung-Chiang Hsi
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Patent number: 11665911Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower interconnect disposed within a dielectric structure over a substrate. A memory device includes a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the lower interconnect. A sidewall spacer includes an interior sidewall that continuously extends from along an outermost sidewall of the top electrode to below an outermost sidewall of the bottom electrode. The sidewall spacer further includes an outermost sidewall that extends from a bottom surface of the sidewall spacer to above a top of the bottom electrode.Type: GrantFiled: July 30, 2021Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuan-Tai Tseng, Chung-Chiang Min, Shih-Chang Liu
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Publication number: 20230155002Abstract: Embodiments provide a replacement metal gate in a FinFET or nanoFET which utilizes a conductive metal fill. The conductive metal fill has an upper surface which has a fin shape which may be used for a self-aligned contact.Type: ApplicationFiled: March 22, 2022Publication date: May 18, 2023Inventors: Shih-Hang Chiu, Wei-Cheng Wang, Chung-Chiang Wu, Chi On Chui
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Publication number: 20230140968Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.Type: ApplicationFiled: January 13, 2023Publication date: May 11, 2023Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Publication number: 20230122022Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Publication number: 20230106314Abstract: A method for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.Type: ApplicationFiled: December 7, 2022Publication date: April 6, 2023Inventors: Cheng-Yen TSAI, Hsin-Yi LEE, Chung-Chiang WU, Da-Yuan LEE, Weng CHANG, Ming-Hsing TSAI
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Publication number: 20230107945Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
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Publication number: 20230106214Abstract: The present disclosure relates to a system, a method and a computer-readable medium for rendering a streaming on a user terminal. The method includes rendering the streaming in a first mode, receiving an environment parameter of the user terminal, receiving a timing when the user terminal closes the streaming, determining a threshold value of the environment parameter based on the timing the user terminal closes the streaming, receiving an updated environment parameter of the user terminal, and rendering the streaming in a second mode if the updated environment parameter meets the threshold value. The second mode includes fewer data objects than the first mode or includes a downgraded version of a data object in the first mode for the rendering. The present disclosure can customize the rendering mode for each user and maximize the satisfaction of viewing streaming for each user.Type: ApplicationFiled: August 4, 2022Publication date: April 6, 2023Inventors: Yung-Chi HSU, Chung-Chiang HSU, Shao-Yuan WU, Ming-Che CHENG
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Publication number: 20230100433Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer is disposed on the first electrode. A second electrode overlies the data storage layer. A buffer layer is disposed between the data storage layer and the second electrode.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Chung-Chiang Min, Chang-Chih Huang, Yuan-Tai Tseng, Kuo-Chyuan Tzeng, Yihuei Zhu
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Publication number: 20230065193Abstract: The present disclosure provides compositions and methods for intra-articular delivery of anti-CSF1R antibodies to a tissue that is impacted by a disease that is treatable with CSF1/CSF1R inhibition and/or that expresses CSF1R. It was conventional knowledge that the intra-articular dwell time of proteins in joints is typically a few hours or less. The present disclosure shows, however, that intra-articular delivery of an anti-CSF1R antibody can lead to sustained exposure and pharmacologic activity of the antibody in the joints far beyond a few hours, providing an effective means for targeted and extended delivery of the therapeutic agent.Type: ApplicationFiled: August 22, 2022Publication date: March 2, 2023Inventors: Kirk William Johnson, Laman Alani, Michael Huang, Chung-Chiang Hsu
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Patent number: 11591319Abstract: Small molecule disruptors of Beclin-1/Bc1-2 protein-protein interactions induce autophagy and hence are useful for treating a variety of indications where stimulation of autophagy is therapeutically useful, including cancer, infection immunity, neurodegeneration, longevity.Type: GrantFiled: April 5, 2022Date of Patent: February 28, 2023Assignee: Board of Regents, The University of Texas SystemInventors: Jef De Brabander, Qiren Liang, Beth Levine, Wei-Chung Chiang
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Patent number: 11594610Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.Type: GrantFiled: February 2, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
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Patent number: 11584205Abstract: A silenced guide rail includes a guide rail body, a guide block, and a slideway. The guide rail body includes a beam piece, and the beam piece includes an abutting end. The guide block is connected to one end of the guide rail body, and the guide block includes a docking strip. The docking strip includes a corresponding abutting end corresponding to the abutting end. The abutting end includes a short side and a bevel. A shape of the corresponding abutting end corresponds to a shape formed by the short side and the bevel. The slideway is formed on the beam piece and the docking strip. Therefore, the present disclosure reduces an abnormal noise generated when a guide post passes through a connection between the guide rail body and the guide block, and an effect of eliminating all or most of the abnormal noise may be achieved.Type: GrantFiled: August 23, 2021Date of Patent: February 21, 2023Assignees: HSIN CHONG MACHINERY WORKS CO. LTD., FUZHOU MINGFANG AUTOMOBILE PARTS INDUSTRY CO., LTD.Inventors: Zhi-Wen Ling, Mei-Qing Zheng, Xi Chen, Yuan-Ming Liang, Chi-Ming Huang, Jeffrey Chung-Chiang Hsi
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Patent number: 11563120Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.Type: GrantFiled: October 22, 2020Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su
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Publication number: 20230010065Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.Type: ApplicationFiled: June 7, 2022Publication date: January 12, 2023Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Wei-Cheng Wang, Chia-Wei Chen, Jian-Hao Chen, Kuan-Ting Liu, Chi On Chui
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Patent number: 11549654Abstract: A light guide structure with jagged protrusions is configured in a lighting device of a mobile vehicle. The light guide structure includes a light injecting surface and a light emitting surface. The light emitting surface includes a middle section and two side sections deployed respectively at opposite ends of the middle section. The side sections have a plurality of jagged protrusions forming a light guiding area. The extending direction of the jagged protrusions intersects with the light emitting direction. A light source module forms an irradiation area by the light guide structure, the light guiding area extending the width of both sides of the irradiation area, the beam contour being enlarged evenly. The disclosure also provides a headlight structure, a light source module having the light guide structure and a convex lens configured sequentially in the light emitting direction.Type: GrantFiled: February 1, 2021Date of Patent: January 10, 2023Assignee: TAN DE TECH CO., LTD.Inventors: Chao Pai Lee, Cheng Chih Lai, Chung Chiang Pan
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Patent number: 11538805Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: GrantFiled: November 4, 2020Date of Patent: December 27, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Patent number: 11532509Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.Type: GrantFiled: May 27, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui