Patents by Inventor An-Chung Chiang

An-Chung Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20210327761
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 21, 2021
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • Metal gate scheme for device and methods of forming
    Patent number: 11127836
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau
  • Sidewall spacer structure for memory cell
    Patent number: 11121308
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin
  • Light device with hollow column light guide for vehicle
    Patent number: 11112081
    Abstract: A light device for a vehicle includes an emitting module, a light condensing lens and a light guide. The light guide has a hollow column defining a light incident side and a light output side away from each other, both sides respectively faced to the emitting module and the light condensing lens, and the hollow column in help of the light guide avoiding material degradation phenomena and structure deforming problem and prolonging the life usage compared with other materials such as solid-transparent plastic or silicone.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: September 7, 2021
    Assignee: TAN DE TECH CO., LTD.
    Inventors: Chung Chiang Pan, Cheng Chih Lai, Chao Pai Lee
  • TRANSISTOR HEAT DISSIPATION MODULE AND ASSEMBLY METHOD THEREOF
    Publication number: 20210272876
    Abstract: A transistor heat dissipation module is adapted for at least one transistor. The transistor heat dissipation module includes a heat dissipation member and an elastic member. The heat dissipation member includes a first wall and a second wall opposite to each other and a first connecting member connected to the first wall and the second wall. An accommodating space is formed between the first wall and the second wall. The transistor is disposed in the accommodating space. The elastic member is disposed in the accommodating space and is located between the at least one transistor and the first wall to press the at least one transistor against the second wall. An assembly method of a transistor heat dissipation module is further provided.
    Type: Application
    Filed: April 20, 2020
    Publication date: September 2, 2021
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Cheng-Chung Chiang, Yu-Po Chen, Ping-Ho Chu, Chih-Chun Yu
  • Semiconductor Devices and Methods of Manufacture
    Publication number: 20210273070
    Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 2, 2021
    Inventors: Chia-Ching Lee, Hung-Chin Chung, Chung-Chiang Wu, Hsuan-Yu Tung, Kuan-Chang Chiu, Chien-Hao Chen, Chi On Chui
  • Geometry for threshold voltage tuning on semiconductor device
    Patent number: 11094828
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Word-line structure, memory device and method of manufacturing the same
    Patent number: 11087808
    Abstract: Provided is a word-line structure including a substrate, a word line, and an epitaxial pattern. The word line is embedded in the substrate. The word line includes a conductive layer, a barrier layer, an insulating layer, and a gate dielectric layer. The barrier wraps a lower portion of the conductive layer. The insulating layer wraps an upper portion of the conductive layer. The gate dielectric layer surrounds the insulating layer and the barrier layer to electrically isolate the barrier layer from the substrate. The epitaxial pattern is disposed between the insulating layer and the substrate and in contact with the substrate. A memory device including the word-line structure and a method of manufacturing the same are also provided.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 10, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Li-Ting Wang, Ming-Chung Chiang
  • Method of forming memory cell
    Patent number: 11088202
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a dielectric structure over a substrate. The integrated chip further includes a memory device having a data storage structure disposed between a bottom electrode and a top electrode. The bottom electrode is electrically coupled to the plurality of lower interconnect layers. A sidewall spacer continuously extends from an outermost sidewall of the data storage structure to below an outermost sidewall of the bottom electrode.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Tai Tseng, Chung-Chiang Min, Shih-Chang Liu
  • Selective Hybrid Capping Layer for Metal Gates of Transistors
    Publication number: 20210242081
    Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.
    Type: Application
    Filed: May 27, 2020
    Publication date: August 5, 2021
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee, Chien-Hao Chen, Chi On Chui
  • Highlight processing method using human pose based triggering scheme and associated system
    Patent number: 11080532
    Abstract: A highlight processing method includes: obtaining a frame sequence that includes frames each having image contents associated with at least one object, wherein object pose estimation is performed upon each frame of the frame sequence to generate an object pose estimation result of each frame, and further includes determining at least one of a start point and an end point of a highlight interval, wherein comparison of object pose estimation results of different frames is involved in determination of at least one of the start point and the end point of the highlight interval.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: August 3, 2021
    Assignee: MEDIATEK INC.
    Inventors: Shih-Jung Chuang, Yan-Che Chuang, Chun-Nan Li, Yu-Hsuan Huang, Chih-Chung Chiang
  • Metal gate fill for short-channel and long-channel semiconductor devices
    Patent number: 11075275
    Abstract: Certain embodiments of a semiconductor device and a method of forming a semiconductor device comprise forming a high-k gate dielectric layer over a short channel semiconductor fin. A work function metal layer is formed over the high-k gate dielectric layer. A seamless metal fill layer is conformally formed over the work function metal layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Ching-Hwanq Su, Da-Yuan Lee, Ji-Cheng Chen, Kuan-Ting Liu, Tai-Wei Hwang, Chung-Yi Su
  • MEMORY DEVICE WITH FLAT-TOP BOTTOM ELECTRODES AND METHODS FOR FORMING THE SAME
    Publication number: 20210217811
    Abstract: A memory device including an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a vertical stack containing a bottom electrode, a memory element, a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.
    Type: Application
    Filed: January 15, 2020
    Publication date: July 15, 2021
    Inventor: Chung-Chiang Min
  • Transistor metal gate and method of manufacture
    Patent number: 11056395
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • LIGHT DEVICE WITH HOLLOW COLUMN LIGHT GUIDE FOR VEHICLE
    Publication number: 20210164632
    Abstract: A light device for a vehicle includes an emitting module, a light condensing lens and a light guide. The light guide has a hollow column defining a light incident side and a light output side away from each other, both sides respectively faced to the emitting module and the light condensing lens, and the hollow column in help of the light guide avoiding material degradation phenomena and structure deforming problem and prolonging the life usage compared with other materials such as solid-transparent plastic or silicone.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: CHUNG CHIANG PAN, CHENG CHIH LAI, CHAO PAI LEE
  • ETCH STOP LAYER FOR MEMORY DEVICE FORMATION
    Publication number: 20210134668
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.
    Type: Application
    Filed: August 31, 2020
    Publication date: May 6, 2021
    Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
  • Semiconductor Device and Method
    Publication number: 20210134667
    Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 6, 2021
    Inventors: Chung-Chiang Wu, Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su
  • Extended release suspension formulation of lurasidone
    Patent number: 10987303
    Abstract: The present disclosure relates generally to depot formulations of lurasidone and methods of making depot formulations of lurasidone. The depot formulations include a suspending agent and are highly syringeable.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: April 27, 2021
    Assignee: LifeMax Laboratories, Inc.
    Inventors: Chung-Chiang Hsu, Tzu-Ying Wu, Wei-Hsiang Wang, Chia-Yu Kuo
  • Small molecule inducers of autophagy
    Publication number: 20210115024
    Abstract: Small molecule disruptors of Beclin-1/Bcl-2 protein-protein interactions induce autophagy and hence are useful for treating a variety of indications where stimulation of autophagy is therapeutically useful, including cancer, infection immunity, neurodegeneration, longevity.
    Type: Application
    Filed: December 4, 2020
    Publication date: April 22, 2021
    Applicant: Board of Regents, The University of Texas System
    Inventors: Jef De Brabander, Qiren Liang, Beth Levine, Wei-Chung Chiang
  • SIDEWALL SPACER STRUCTURE FOR MEMORY CELL
    Publication number: 20210111333
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Inventors: Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng, Sheng-Huang Huang, Chia-Hua Lin