Abstract: Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.

Abstract: Provided are high concentration stable formulations of anti-CSF1R/CSF1 antibodies. An example formulation includes 105 to 250 mg/mL of the antibody, 100 mM to 200 mM of arginine glutamate or arginine HCl, 10 mM to 50 mM histidine, and 0.015 to 0.035 w/v % of polysorbate 80, at a pH of 5.4 to 5.6. Also provided are methods of using the formulations for treating diseases.

Abstract: A memory device with hard mask insulator and its manufacturing methods are provided. In some embodiments, the memory device includes a memory cell stack disposed over a substrate. The memory cell stack includes a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is disposed over the top electrode layer, and a first metal hard masking layer disposed over the first insulating layer.

Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

Abstract: A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

Abstract: A memory device including an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a vertical stack containing a bottom electrode, a memory element, a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A memory cell with hard mask insulator and its manufacturing methods are provided. In some embodiments, a memory cell stack is formed over a substrate having a bottom electrode layer, a resistance switching dielectric layer over the bottom electrode layer, and a top electrode layer over the resistance switching dielectric layer. A first insulating layer is formed over the top electrode layer. A first metal hard masking layer is formed over the first insulating layer. Then, a series of etch is performed to pattern the first metal hard masking layer, the first insulating layer, the top electrode layer and the resistance switching dielectric layer to form a first metal hard mask, a hard mask insulator, a top electrode, and a resistance switching dielectric.

Abstract: The present invention provides a sensing device and a keycap. The sensing device includes a sensing unit and a base unit. The sensing unit includes a first sensing unit surface having a binding area and a non-binding area, wherein the binding area and the non-binding area do not overlap with each other and correspond to each other in shape. The base unit includes a first base unit surface having a contact area and a non-contact area, wherein the contact area and the non-contact area do not overlap with each other and correspond to each other in shape. The sensing unit is attached to the contact area of the base unit by the binding area; and sides of the sensing unit and the base unit side are flush with each other. The sensing device can function as a keycap.

Abstract: A transistor heat dissipation module is adapted for at least one transistor. The transistor heat dissipation module includes a heat dissipation member and an elastic member. The heat dissipation member includes a first wall and a second wall opposite to each other and a first connecting member connected to the first wall and the second wall. An accommodating space is formed between the first wall and the second wall. The transistor is disposed in the accommodating space. The elastic member is disposed in the accommodating space and is located between the at least one transistor and the first wall to press the at least one transistor against the second wall. An assembly method of a transistor heat dissipation module is further provided.

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.

Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes a memory device disposed over a lower interconnect within one or more lower inter-level dielectric (ILD) layers over a substrate. An upper ILD layer laterally surrounds the memory device. An etch stop layer is disposed along a sidewall of the memory device and over an upper surface of the one or more lower ILD layers. An upper interconnect is arranged along opposing sides of the memory device. The upper interconnect rests of an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.

Abstract: A vehicle signal light structure includes a light guide, two light source modules, and a collimator. The light guide includes an elongated light output surface, a light incident surface being disposed at both sides of the light output surface, and a light guide surface being disposed below the light output surface. The light guide surface is tilted upward from the light incident surface to the center of the light guide. The light guide surface includes a plurality of V-shaped microstructures defining a light guide structure. The light source modules are disposed at the light incident surface of the light guide. The collimator has a light incident surface disposed at the light output surface of the light guide. A light passing through the light incident surface of the light guide is reflected by the light guide surface and directs to the light output surface, then, is collimated by the collimator.

Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a first dielectric layer having a first region and a second region. A bottom electrode is at least partially arranged within the first region of the first dielectric layer. A memory element is over the bottom electrode and a top electrode is over the memory element. A second dielectric layer is over at least the first region of the first dielectric layer. The second dielectric layer surrounds the memory element and at least a part of the top electrode. A third dielectric layer is over the second region of the first dielectric layer and laterally adjacent to the second dielectric layer. A conductive interconnect is in the third dielectric layer and the second region of the first dielectric layer. The first dielectric layer has a different non-zero thickness within the first region than within the second region.

Abstract: A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a lower dielectric layer over a conductive wire. A stack of memory layers is formed within the lower dielectric layer and over the conductive wire. The stack of memory layers comprises a top electrode, a bottom electrode, and a data storage layer between the top electrode and the bottom electrode. A removal process is performed on the stack of memory layers to define a programmable metallization cell that comprises the top electrode, the bottom electrode, and the data storage layer. The programmable metallization cell comprises a central region and a peripheral region that extends upwardly from the central region. A top surface of the programmable metallization cell and a top surface of the lower dielectric layer are coplanar.