Patents by Inventor An Chung

An Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240193958
    Abstract: A processing method for vehicle surround view, a vehicle surround view system and an in-vehicle processing device are provided. The processing method for vehicle surround view includes the following steps: obtaining a first exterior image and a second exterior image; recognizing a first interest object in the first exterior image and a second interest object in the second exterior image; fitting the first interest object to a first geometric contour and fitting the second interest object to a second geometric contour; applying the first geometric contour and the second geometric contour on a 3D model, to obtain a ground point, a first contour position and a second contour position; obtaining a merged contour position according to the ground point; and projecting the first interest object or the second interest object at the merged contour position on a vehicle surround image.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 13, 2024
    Inventors: Yen-Chun CHEN, Jiun-Shiung Chen, Chien-Chung Lee, Chi-Min Weng, Chuen-Ning Hsu
  • Publication number: 20240193755
    Abstract: A pattern defect inspection device includes an inspection apparatus inspecting a pattern on a substrate, a database storing a pattern layout including a plurality of defect patterns from the inspection apparatus, a preset field of view (FOV) size, and a target measurement number, and a processor setting a plurality of inspection regions of the inspection apparatus based on the pattern layout, wherein the processor includes a defect search unit searching for a region defect pattern existing in any one of a plurality of inspection regions in the pattern layout, an inspection region aligning unit arranging the plurality of inspection regions based on the region defect pattern, an overlapping region removal unit removing an overlapping region from the plurality of inspection regions, and an inspection region selecting unit selecting an inspection region other than the overlapping region, among the plurality of inspection regions, as a final inspection region.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 13, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jungkee CHOI, Noyoung CHUNG
  • Publication number: 20240193984
    Abstract: Provided is a full-screen display device with unit pixel having function for emitting and receiving light, including a water-oxygen barrier layer, a protective panel, a plurality of unit pixels, a light-shielding layer, and a plurality of lens. At least one of the unit pixels has a light-emitting area inside, and has a light-sensing area inside or outside. For biometrics recognition, the light-emitting area emits an incident light, which penetrates through the water-oxygen barrier layer and scatters outwardly by at least one of the lenses. The scattered incident light penetrates through the protective panel, and reflected by a test object. The reflected light penetrates through the protective panel and is converged by at least one of the lenses. The converged reflected light penetrates through the water-oxygen barrier, and the light-sensing area receives and converts the reflected light to an image electrical signal.
    Type: Application
    Filed: November 6, 2023
    Publication date: June 13, 2024
    Inventors: Chun-Yu Lee, Jun-Wen Chung
  • Publication number: 20240194279
    Abstract: A system can include a plurality of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices, to perform operations comprising: determining whether a parameter of a power supply of the volatile memory device satisfies a threshold criterion; responsive to determining that the parameter of the power supply satisfies the threshold criterion, modifying a value of a parameter of a program operation; and programming, using the modified value of the parameter, designated data stored on the volatile memory device to a designated location on the non-volatile memory device.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 13, 2024
    Inventors: Tomer Tzvi Eliash, Yu-Chung Lien
  • Publication number: 20240194418
    Abstract: A method of fabricating a halide perovskite having a general formula of ABX3, wherein A, B, and X are inorganic elements and X is a halide, the method including a vapor-liquid-solid process triggered by a catalyst formed from a halide precursor of inorganic element B. A ABX3 nanowire formed by the method and a photoelectronic device with the ABX3 nanowire.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 13, 2024
    Inventors: Chung Yin Johnny Ho, Dengji Li, You Meng, Yini Zheng
  • Publication number: 20240190228
    Abstract: A battery pack mounting structure for vehicles, includes a frame side member extending in a front and rear direction on each side of a vehicle to form a chassis frame, a battery disposed to be overlapped horizontally on inside of both frame side members, and a battery case enclosing the battery therein, wherein a case side portion provided on a side of the battery case is coupled to a lower side of the frame side member.
    Type: Application
    Filed: May 10, 2023
    Publication date: June 13, 2024
    Applicants: Hyundai Motor Company, Kia Corporation
    Inventors: Won Hae LEE, Nam Ho KIM, Dae Ki JEONG, Su Jin LEE, Jun Woo PARK, Jeong Hoon HAN, Eun Bi KIM, Sun Keun PARK, Byung Joo CHUNG, Seung Hak LEE, Seung Min JEONG
  • Publication number: 20240192434
    Abstract: An anti-peep light source module and an anti-peep display device having an anti-peep function and good image quality are provided. The anti-peep light source module includes a light guide plate, a first light emitting element, a second light emitting element, a plurality of optical microstructures and a first surface. The light guide plate has a first light incident surface and a second light incident surface. Each of the optical microstructures has a first optical surface facing the first light incident surface and a second optical surface facing the second light incident surface. A magnitude of a first included angle between the first optical surface and the first surface and a magnitude of a second included angle between the second optical surface and the first surface gradually change as getting farther away from the first surface.
    Type: Application
    Filed: December 5, 2023
    Publication date: June 13, 2024
    Applicants: CHAMP VISION DISPLAY INC., Coretronic Corporation
    Inventors: Hsin-Hung Lee, Chung-Hao Wu, Chun-Chien Liao, Ming-Huei Shiu
  • Publication number: 20240194407
    Abstract: Provided are a dielectric material, a device including the same, and a method of preparing the dielectric material. The dielectric material includes a polycrystalline oxide including a plurality of crystal grain bulks and grain boundaries located between the plurality of crystal grain bulks, and the polycrystalline oxide includes an indium dopant in the grain boundaries.
    Type: Application
    Filed: June 22, 2023
    Publication date: June 13, 2024
    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sung-Yoon CHUNG, Ji-Sang An
  • Publication number: 20240194523
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect dielectric layer over a substrate. An interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. A protective layer surrounds the interconnect via. The interconnect via vertically extends through the protective layer to below a bottom of the protective layer. The protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao
  • Publication number: 20240194744
    Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 13, 2024
    Inventors: Yi-Cheng CHIU, Tian Sheng LIN, Hung-Chou LIN, Yi-Min CHEN, Chiu-Hua CHUNG
  • Publication number: 20240195082
    Abstract: An antenna structure includes a ground element, a feeding radiation element, a first radiation element, a second radiation element, a shorting radiation element, a third radiation element, and a fourth radiation element. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the feeding radiation element. The second radiation element and the first radiation element substantially extend in opposite directions. The feeding radiation element is further coupled through the shorting radiation element to the ground element. The third radiation element is coupled to the ground element. The third radiation element is adjacent to the first radiation element. The fourth radiation element is coupled to the ground element. The fourth radiation element is adjacent to the second radiation element.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 13, 2024
    Inventors: Yi-Chih LO, Chung-Ting HUNG, Chun-Yuan WANG, Chun-I CHEN, Jing-Yao XU, Yan-Cheng HUANG, Chu-Yu TANG
  • Publication number: 20240196119
    Abstract: A rogue ONU detection and recovery method in a PON network includes steps of: monitoring upstream signals transmitted from a plurality of ONUs to an OLT to acquire LOS signal information and FEC error information; sensing an operation of the rogue ONU in the PON network on the basis of the LOS signal information and the FEC error information; and deactivating at least one of the plurality of ONUs and recovering the rogue ONU to a normal ONU according to whether or not the operation of the rogue ONU is released.
    Type: Application
    Filed: August 9, 2023
    Publication date: June 13, 2024
    Inventors: Kwang Ok KIM, Kyeong Hwan DOO, Hwan Seok CHUNG
  • Publication number: 20240196287
    Abstract: Disclosed are radio bearer management method and apparatus for multi-radio multi-connectivity. A method of a terminal may comprise: transmitting UP data to at least one node among an MN or SN through a first DRB; and in response to identifying a UL coverage loss in the second SN, determining switching from the first DRB to a second DRB based on a bearer switching rule.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 13, 2024
    Inventors: Sun Mi JUN, II Gyu KIM, Jung Im KIM, Jun Sik KIM, SoonGi PARK, Sung Cheol CHANG, Hee Sang CHUNG, Yong Seouk CHOI
  • Publication number: 20240194927
    Abstract: Discussed is a cutting device configured to cut at least a portion of an uncoated portion of an electrode assembly that includes an electrode cell body portion in which a separator, and a first electrode sheet and a second electrode sheet are wound in a state of being stacked, and the uncoated portion on which an active material layer is not coated is provided on an end portion of at least one of the first electrode sheet and the second electrode sheet in a width direction thereof. The cutting device can include a cutter portion configured to form a cut line in the uncoated portion, the cut line extending in an axial direction of the electrode assembly, and the cutter portion forming the cut line while moving in the axial direction.
    Type: Application
    Filed: April 7, 2022
    Publication date: June 13, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Minwoo KIM, Do Gyun KIM, Joo Young CHUNG
  • Publication number: 20240194572
    Abstract: A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a cross-sectional view and a second land section having a second height in the cross-sectional view that is different than the first height. A mold encapsulant is disposed adjacent a lateral portion of the first land section and is disposed below a bottom portion of the second land section. A semiconductor die is attached to the substrate, and includes a first major surface, a second major surface opposing the first major surface, and an outer perimeter. The semiconductor die further includes a bonding structure disposed adjacent the first major surface, which is coupled to the second land section such that the first land section is disposed outside the perimeter of the semiconductor die A mold member encapsulates at least portions of the semiconductor die.
    Type: Application
    Filed: February 17, 2024
    Publication date: June 13, 2024
    Applicant: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Kyoung Yeon LEE, Byong Jin KIM, Jae Min BAE, Hyung Il JEON, Gi Jeong KIM, Ji Young CHUNG
  • Publication number: 20240194656
    Abstract: A display apparatus including a plurality of display modules each including a module substrate and a plurality of light emitting devices mounted on the module substrate, and a support substrate on which the display modules are disposed and including conductive members, in which the module substrates includes a plurality of recesses depressed from at least one end surface of the module substrate, and connection electrodes formed in the recesses, and the light emitting devices are electrically connected to the conducive members of the support substrate through the connection electrodes.
    Type: Application
    Filed: January 22, 2024
    Publication date: June 13, 2024
    Applicant: Seoul Semiconductor Co., Ltd.
    Inventor: Chung Hoon LEE
  • Publication number: 20240194549
    Abstract: A semiconductor device assembly is provided. The assembly includes a support layer with an inside surface, a semiconductor device, and an encapsulant material. The encapsulant material includes a bulk material and thermally conductive nanoparticles, each nanoparticle having an electrically insulative shell and an electrically conductive core. The semiconductor device is disposed on the inside surface of the support layer, the thermally conductive nanoparticles are evenly distributed throughout the bulk material, and the encapsulant material at least partially encapsulates the semiconductor device.
    Type: Application
    Filed: November 9, 2023
    Publication date: June 13, 2024
    Inventors: Min Hua Chung, Chong Leong Gan
  • Publication number: 20240194767
    Abstract: Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.
    Type: Application
    Filed: January 29, 2024
    Publication date: June 13, 2024
    Inventors: Jen-Hong Chang, Yuan-Ching Peng, Chung-Ting Ko, Kuo-Yi Chao, Chia-Cheng Chao, You-Ting Lin, Chih-Chung Chang, Yi-Hsiu Liu, Jiun-Ming Kuo, Sung-En Lin
  • Publication number: 20240194764
    Abstract: A semiconductor device includes semiconductor channel members disposed over a substrate, a gate dielectric layer disposed on and wrapping around the semiconductor channel members, a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor channel members, a source/drain (S/D) epitaxial layer in physical contact with the semiconductor channel members, and a dielectric spacer interposing the S/D epitaxial layer and the gate dielectric layer. The dielectric spacer includes a first dielectric layer in physical contact with the gate dielectric layer and a second dielectric layer in physical contact with the first dielectric layer. The first dielectric layer has a dielectric constant higher than that of the second dielectric layer. The second dielectric layer separates the first dielectric layer from physically contacting the S/D epitaxial layer.
    Type: Application
    Filed: February 19, 2024
    Publication date: June 13, 2024
    Inventors: Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Publication number: 20240194787
    Abstract: A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.
    Type: Application
    Filed: February 19, 2024
    Publication date: June 13, 2024
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng