Abstract: In a method for unlocking an object of an electronic device, an unlocking rule is preset to unlock the object. After movement signals are received from a touch screen of the electronic device, a quantity of segments displayed on the touch screen generated by the movement signals and a quantity of areas of the touch screen partitioned by the obtained segments are obtained. When a touch signal on one area of the obtained areas is received, a sequence number of the area from which the touch signal is received is calculated. The object of the electronic device is unlocked when the object is authorized to be unlocked according to the preset unlocking rule, the quantity of the obtained segments, the quantity of the obtained areas, and the sequence number of the area from which the touch signal is received.

Abstract: A reference frequency setting method of a memory storage apparatus including the following steps is provided. A setting code is read from a memory module or a storage unit by a first signal transmission path and stored into a register circuit. The setting code includes a first setting information. Whether the data having a specific frequency is inputted is detected. If not, the setting code stored in the register circuit is read, such that an oscillator circuit module of the memory storage apparatus generates a first reference frequency based on the first setting information. If yes, the setting code stored in the register circuit is updated by a second signal transmission path, and the updated setting code is read, such that the oscillator circuit module generates a second reference frequency based on a second setting information. The updated setting code includes the second setting information.

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract: A signal processing method, a connector and a memory storage device are provided. The signal processing method is for the connector which does not include a crystal oscillator. The signal processing method includes: receiving a first signal stream from a host system; tracking a transmission frequency of the first signal stream, and obtaining a frequency shift quantity of the first signal stream relative to the transmission frequency; determining if a spread spectrum operation is performed on the first signal stream according to the frequency shift quantity to generate a determination result; generating a second signal stream according to the determination result and the transmission frequency. Accordingly, the spread spectrum operation is handled under the situation without a crystal oscillator.

Abstract: A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.

Abstract: The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX). The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.

Abstract: A method and a data transceiving system for generating a reference clock signal are provided. The data transceiving system comprises a voltage controlled oscillator, a phase lock loop (PLL) unit, and a data receiver. The voltage controlled oscillator is used to generate a reference clock signal. The PLL unit is used to increase a clock frequency of the reference clock signal to generate a PLL clock signal. The data receiver is used to compare the PLL clock signal with a clock signal of an input data stream, so as to output a voltage adjusting signal to the voltage controlled oscillator. The voltage controlled oscillator adjusts the clock frequency of the reference clock signal to be generated according to the reference clock signal, so as to lock the clock frequency of the PLL clock signal to a base frequency of the clock signal of the input data stream.

Abstract: A laser-optical position detecting module with a laser as a light source is disclosed, which includes a laser mode conversing assembly, having a laser source capable of emitting a time-modulated laser beam; a laser mode conversing unit, used to expand the time-modulated laser beam to a two-dimension sensing plane; a drive control unit, adopted for driving the laser source to emit the time-modulated laser beam; and a detector matrix. The laser mode conversing unit has a phase delay device and a passive optical device capable of reflecting the light; so that, through the laser mode conversing unit, the laser-optical position detecting module can expand the light emitted by the laser source to the two-dimension sensing plane without using any other mechanical scanning.

Abstract: In a method for monitoring a second mobile device using a first mobile device and wireless communication, a prompting file, a time interval, and a name of a second communication module of the second mobile device are set in the first mobile device. A first communication module of the first mobile device searches for discoverable devices within a predetermined coverage area of the first mobile device. Each found discoverable device is entered in a device list of the first mobile device. If the second communication module is found, a timer starts timing the time interval. After the time interval has elapsed, the first communication module searches for the discoverable devices again, for updating the device list. If the second communication module is not in the updated device list, the prompting file is outputted to alert a user of the first mobile device.

Abstract: A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.

Abstract: A reference frequency setting method of a flash memory storage apparatus is provided. The flash memory storage apparatus includes a flash memory module, a storage unit, and an oscillator circuit without a crystal. The reference frequency setting method includes following steps. Whether a setting code is stored in the flash memory module or the storage unit is determined, wherein the setting code includes information of a reference frequency. If the setting code is stored in the flash memory module, the setting code is read to allow the oscillator circuit to generate the reference frequency according to the setting code. A memory controller and a flash memory storage apparatus using the reference frequency setting method are also provided.

Abstract: The present invention relates to a laser-optical position detecting module with a laser light source, comprising: laser mode conversing assembly, having a laser source capable of emitting a time-modulated laser beam; a laser mode conversing unit, used to expand the time-modulated laser beam to a two-dimension sensing plane; a drive control unit, adopted for driving the laser source to emit the time-modulated laser beam; and a detector matrix, used for detecting the. The laser mode conversing unit has a phase delay device and a passive optical device capable of reflecting the light; so that, through the laser mode conversing unit, the laser-optical position detecting module can expand the light emitted by the laser source to the two-dimension sensing plane without using any other mechanical scanning; moreover, it make the energy of the light emitted by the laser source not easily decays, so as to maintain the accuracy of light detection.

Abstract: The configurations of an electro-optic Bragg deflector and the methods of using it as a laser Q-switch in a Q-switched laser and in a Q-switched wavelength-conversion laser are provided. As a first embodiment, the electro-optic Bragg deflector comprises an electrode-coated electro-optic material with one of a 1D and a 2D spatially modulated electro-optic coefficient. When a voltage is supplied to the electrodes, the electro-optic material behaves like a Bragg grating due to the electro-optically induced spatial modulation of the refractive index. The second embodiment relates to an actively Q-switched laser, wherein the electro-optic Bragg deflector functions as a laser Q-switch. The third embodiment of the present invention combines the Q-switched laser and a laser-wavelength converter to form a Q-switched wavelength-conversion laser, wherein the EO Bragg deflector can be monolithically integrated with a quasi-phase-matching wavelength converter in a fabrication process.

Abstract: An apparatus is provided, for reducing power consumption in a system operating in a power saving mode, comprising a controller, an oscillator circuit and a voltage regulator. The controller provides a first control signal and a second control signal. The oscillator circuit, connected to the controller, wherein the controller controls the oscillator circuit according to the second control signal. The voltage regulator providing electric power to the oscillator circuit, connected to the controller, wherein the controller controls the voltage regulator according to the first control signal.

Abstract: A method and a data transceiving system for generating a reference clock signal are provided. The data transceiving system comprises a voltage controlled oscillator, a phase lock loop (PLL) unit, and a data receiver. The voltage controlled oscillator is used to generate a reference clock signal. The PLL unit is used to increase a clock frequency of the reference clock signal to generate a PLL clock signal. The data receiver is used to compare the PLL clock signal with a clock signal of an input data stream, so as to output a voltage adjusting signal to the voltage controlled oscillator. The voltage controlled oscillator adjusts the clock frequency of the reference clock signal to be generated according to the reference clock signal, so as to lock the clock frequency of the PLL clock signal to a base frequency of the clock signal of the input data stream.

Abstract: The configurations of an electro-optic Bragg deflector and the methods of using it as a laser Q-switch in a Q-switched laser and in a Q-switched wavelength-conversion laser are provided. As a first embodiment, the electro-optic Bragg deflector comprises an electrode-coated electro-optic material with one of a 1D and a 2D spatially modulated electro-optic coefficient. When a voltage is supplied to the electrodes, the electro-optic material behaves like a Bragg grating due to the electro-optically induced spatial modulation of the refractive index. The second embodiment relates to an actively Q-switched laser, wherein the electro-optic Bragg deflector functions as a laser Q-switch. The third embodiment of the present invention combines the Q-switched laser and a laser-wavelength converter to form a Q-switched wavelength-conversion laser, wherein the EO Bragg deflector can be monolithically integrated with a quasi-phase-matching wavelength converter in a fabrication process.

Abstract: An electronic device comprises a body, a first image capturing element, a cover and a arm. The body comprises a first surface and a second surface, with the first surface opposite to the second surface. The first image capturing element is disposed on the first surface. The cover is connected to the body, movable between a first cover position and a second cover position, wherein the cover covers the first image capturing element when the cover is in the first cover position, and the first image capturing element is actuated when the cover is in the second cover position. The arm is connected to the cover, pivoting between a first position and a second position, wherein when the arm is in the second position, a recording medium is received on a first end of the arm, and the first image capturing element captures an image data therefrom.

Abstract: The invention relates to a low power module, and in particular, to a low power module applied in a station of a wireless communication system. A low power module includes a first MAC module, a second MAC module, a low power switch register, a control register unit, a slow clock generator, and a multiplexer (MUX). The first and second MAC module transmits and receives packets in a normal operational mode and a power save mode, respectively. The low power switch register switches a current mode to another mode. The control register unit controls the RF/BB module and the clock generator under the control of the low power switch register. The slow clock generator generates a slow operational clock for the second MAC module in the power save mode. The MUX chooses the normal operational or the slow operational clock periodically as a clock of the second MAC module according to the control register unit.

Abstract: An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.

Abstract: A method and system for automated discovery of logical network elements in a communications network speeds up and reduces the cost of discovering network elements and mapping network topology of network inter-connections. The method comprises the steps of building a cache of protection mechanisms in the communications network, building a network graph based on physical links of the communications network, traversing the network graph, comprising the step of, at each vertex of the network graph, determining whether there is a deterministic path that leads to a next vertex of the network graph, performing a depth first search on the network graph to determine connected components of the network graph, and creating the logical network elements based on the connected components of the network graph.