Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes a memory device disposed over a lower interconnect within one or more lower inter-level dielectric (ILD) layers over a substrate. An upper ILD layer laterally surrounds the memory device. An etch stop layer is disposed along a sidewall of the memory device and over an upper surface of the one or more lower ILD layers. An upper interconnect is arranged along opposing sides of the memory device. The upper interconnect rests of an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

Abstract: This document describes techniques and apparatuses directed at preventing eavesdropping resources from acquiring unauthorized data via mechanically excitable sensors. In aspects, an electronic device includes a privacy manager configured to analyze one or more signals generated by a mechanically excitable sensor. Responsive to the analysis, the privacy manager may extract unauthorized data from the one or more signals based on a signal received at a mechanical transducer, and further based on calibration data collected during an interaction between the mechanically excitable sensor and the mechanical transducer during a prior calibration sequence.

Abstract: A pulse width modulation (PWM) driver and an operation method thereof are provided. The PWM driver includes a PWM generating circuit and multiple driving channels. The PWM generating circuit generates multiple PWM signals. The driving channels drive multiple light emitting elements of a light emitting element array. Each of the driving channels includes a PWM selection circuit. The PWM selection circuits are coupled to the PWM generating circuit to receive the PWM signals. Each of the PWM selection circuits selects a PWM signal from the PWM signals according to corresponding sub-pixel data. The selected PWM signal is output to at least one corresponding light emitting element among the light emitting elements.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and the fin structure includes a plurality of nanostructures stacked in a vertical direction. The semiconductor device structure includes a gate structure formed over the fin structure, and an S/D structure formed adjacent to the gate structure. The semiconductor device structure includes a first via formed adjacent to the S/D structure, and a first contact structure formed over the S/D structure. The semiconductor device structure includes a second contact structure formed below the S/D structure, and the first via is in direct contact with the first contact structure and the second contact structure.

Abstract: An electronic device and a method of controlling an electronic device are provided. The method includes obtaining an image comprising a text through a camera, identifying an input text, among texts included in the image, to be translated, obtaining a first vector corresponding to the input text by inputting the identified input text to an encoder of a translation model, identifying whether additional information is necessary to translate the input text by inputting the first vector to a first artificial intelligence model trained to translate the input text, based on identification that the additional information is necessary, identifying additional information among the at least one context information by inputting the first vector and at least one context information obtained from the image, and obtaining an output text corresponding to the input text by inputting the first vector and the identified additional information to a decoder of the translation model.

Abstract: A system for evaluating performance of a driver of a vehicle with an electronic control unit is provided. The system includes an evaluation processor configured to access driving dynamics data regarding operation of the vehicle, and a driver monitoring sensor in communication with the evaluation processor to generate driver status data that relates to a position, orientation, or condition of the driver. One or more external monitoring sensors are in communication with the evaluation processor to generate external interaction data relating to interaction of the driver with an external environment. The evaluation processor is configured to generate a driver rating based upon the driving dynamics data and the driver status data and the external interaction data. A method for evaluating performance of a driver of a vehicle is also provided.

Abstract: Provided is a memory device including a substrate, a plurality of first stack structures, and a plurality of second stack structures. The substrate includes an array region and a periphery region. The first stack structures are disposed on the substrate in the array region. Each first stack structure sequentially includes: a first tunneling dielectric layer, a first floating gate, a first inter-gate dielectric layer, a first control gate, a first metal layer, a first cap layer, and the first stop layer. The second stack structures are disposed on the substrate in the periphery region. Each second stack structure sequentially includes: a second tunneling dielectric layer, a second floating gate, a second inter-gate dielectric layer, a second control gate, a second metal layer, a second cap layer, and the second stop layer. The first stack structures have a pattern density greater than a pattern density of the second stack structures.

Abstract: Disclosed are ethylene polymer compositions containing a homogeneously-branched first ethylene polymer component and 15-35 wt. % of a homogeneously-branched second ethylene polymer component of higher density than the first ethylene polymer component. The ethylene polymer composition can be characterized by a density from 0.912 to 0.925 g/cm3, a ratio of Mw/Mn from 2 to 5, a melt index less than 2 g/10 min, and a CY-a parameter at 190° C. from 0.35 to 0.7. These polymer compositions have the excellent dart impact strength and optical properties of a metallocene-catalyzed LLDPE, but with improved machine direction tear resistance, and can be used in blown film and other end-use applications. Further, methods for improving film Elmendorf tear strength also are described.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: A method for manufacturing a fucoidan cosmetic composition includes: washing mozuku to eliminate residual salt and impurities; adding citric acid to the washed mozuku and pulverizing the mozuku; adding water to the pulverized mozuku and performing reflux extraction to obtain a high molecular weight fucoidan; adding a neutralizing agent to the high molecular weight fucoidan for neutralization; adding diatomite to the neutralized high molecular weight fucoidan and causing a reaction for 30 minutes for deodorization; filtering the deodorized high molecular weight fucoidan to eliminate insoluble substances; adding a lactic acid bacterium to the high molecular weight fucoidan removed of the insoluble substances and causing fermentation to obtain a low molecular weight fucoidan; concentrating the purified low molecular weight fucoidan with a reduced pressure evaporator; and powdering the concentrated low molecular weight fucoidan through freeze drying.

Abstract: An electrophoretic display device, including an electrophoretic display panel and a display driving module, is provided. The display driving module is coupled to the electrophoretic display panel and is used for driving the electrophoretic display panel. The display driving module generates multiple first grayscale images according to multiple color pixel values of multiple color pixels corresponding to multiple colors of a color image. The display driving module captures multiple grayscale values of multiple locations of multiple first sub-pixels of the first grayscale images according to multiple locations of multiple mask sub-pixels corresponding to the colors in a mask image to generate multiple second grayscale images. The display driving module synthesizes the second grayscale images to generate a synthesized image. The display driving module drives the electrophoretic display panel according to the synthesized image.

Abstract: An electronic device may include a display, a housing member at least partially surrounding the display and including a first segment defining a first portion of an exterior surface of the electronic device, a second segment defining a second portion of the exterior surface of the electronic device and configured to function as an antenna, and a bridge segment structurally and conductively coupling the first segment to the second segment. The electronic device may also include a molded element positioned between the first segment and the second segment and defining a third portion of the exterior surface of the electronic device.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, and a dipole layer surrounding each first semiconductor layer of the one or more first semiconductor layers, wherein the dipole layer comprises germanium. The structure also includes a capping layer surrounding and in contact with the dipole layer, wherein the capping layer comprises silicon, one or more second semiconductor layers disposed adjacent the one or more first semiconductor layers.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes first and second pair of source/drain regions disposed on a substrate, first and second nanostructured channel regions, and first and second gate structures with effective work function values different from each other. The first and second gate structures include first and second high-K gate dielectric layers, first and second barrier metal layers with thicknesses different from each, first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively, a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer, and a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.

Abstract: The present application relates to ligands targeted to epidermal growth factor receptor (EGFR) and compositions for use in treating tumors. Specifically, a ligand targeted to EGFR is disclosed. The ligand comprises a heavy chain variable domain and a light chain variable domain. The ligand may be selected from the group consisting of a single chain variable fragment, a fusion protein, a monoclonal antibody, and an antigen-binding fragment thereof. The ligand may be conjugated to a liposome or a nanoparticle that encapsulates at least one chemotherapeutic agent to form a ligand-targeted liposomal or nanoparticle drug. Also disclosed are conjugates and formulations for use in treating tumors such as squamous cell carcinoma of head and neck. A method for making a ligand-targeted liposomal drug is also disclosed. The drug may be a chemotherapeutic agent selected from the group consisting of doxorubicine and vinorelbine.

Abstract: A semiconductor structure is provided. The semiconductor structure may include a transistor structure, the transistor structure may include a gate region arranged over an upper surface of a substrate and extending substantially in a first direction that is perpendicular to the upper surface of the substrate; a first source/drain region over the upper surface of the substrate; a second source/drain region over the upper surface of the substrate; and a channel region vertically extending in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region covers a sidewall of the channel region.

Abstract: Provided is a steel reinforcement including an amount of 0.07 to 0.43 wt % of carbon (C), an amount of 0.5 to 2.0 wt % of manganese (Mn), an amount of 0.05 to 0.5 wt % of silicon (Si), an amount greater than 0 and less than or equal to 0.5 wt % of chromium (Cr), an amount greater than 0 and less than or equal to 4.5 wt % of copper (Cu), an amount greater than 0 and less than or equal to 0.003 wt % of boron (B), an amount greater than 0 and less than or equal to 0.25 wt % of vanadium (V), an amount greater than 0 and less than or equal to 0.012 wt % of nitrogen (N), an amount greater than 0 and less than or equal to 0.03 wt % of phosphorus (P), an amount greater than 0 and less than or equal to 0.03 wt % of sulfur (S), an amount of 0.01 to 0.5 wt % of the sum of one or more of nickel (Ni), niobium (Nb) and titanium (Ti), the balance of iron (Fe), and other inevitable impurities. A final microstructure includes ferrite, bainite, pearlite, retained austenite, and precipitates comprising copper.

Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.