Abstract: An uninterruptible power supply and method for controlling same are disclosed. The controlling method includes the steps of bypassing the first AC power to the output terminal via the bypass loop and the switch and converting a second AC power having a voltage, phase and frequency substantially equal to that of the first AC power by an inverter when the first AC power is normal; and switching the second AC power to the output terminal via the switch when the phase or frequency of the first AC power is changed so as to generate a difference value between the first AC power and the second AC power and the difference value is larger than a predetermined difference value.

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

Abstract: A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the second side of the phase change element. The memory includes a circuit for precharging the bit line and one of selecting only the first access device to program the phase change element to a first state and selecting both the first access device and the second access device to program the phase change element to a second state.

Abstract: A method for programming a mixed nonvolatile memory array having a plurality of mixed memory cells, wherein each mixed memory cell includes a depletion mode memory cell and an enhanced mode memory cell. The method comprises steps of programming the enhanced mode memory cell in a way of channel hot carrier and programming the depletion mode memory cell in a way of band-to-band tunneling hot carrier.

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract: A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.

Abstract: A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.

Abstract: A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.

Abstract: The invention relates to a method and a system for information corresponding to a geographical position. The method includes the following steps. First, a plurality of words are captured from electronic information. Then, position information conforming to a specific address format is searched out in the captured words. Furthermore, the position information is converted to latitude and longitude data.

Abstract: Remote controllers and systems thereof are disclosed. The remote controller remotely operates a receiving host, in which the receiving host provides voice input and voice recognition functions. The remote controller comprises a first input unit and a second input unit for generating a voice input request and a voice recognition request. The generated voice input and voice recognition requests are then sent to the receiving host, thereby forcing the receiving host to perform the voice input and voice recognition functions.

Abstract: A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.

Abstract: Memory devices are disclosed. One example of a memory device may include two layers of memory arrays each containing at least four memory cells. In particular, the memory device includes two word lines commonly shared by the two layers of the memory arrays, with the word lines coupled with the memory cells and providing gate regions of the memory cells. Additionally, a first pair of bit lines cross under the two word lines and providing source and drain regions to the first layer of the two layers of the memory arrays, and a second pair of bit lines cross over the two word lines and providing source and drain regions to the second layer of the two layers of the memory arrays. A first set of channel regions are disposed between the source and drain regions to the first layer of the two layers of the memory arrays, and a second set of channel regions are disposed between the source and drain regions to the second layer of the two layers of the memory arrays.

Abstract: An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.

Abstract: An operating method of a memory array is provided. The operating method includes performing a programming operation.

Abstract: An integrated circuit includes a memory element configured to be programmed to any one of at least three resistance states and a circuit. The circuit is configured to program the memory element to a selected one of the at least three resistance states by applying a pulse to the memory element. The pulse includes one of at least three tail portions wherein each tail portion corresponds to one of the at least three resistance states.

Abstract: A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.

Abstract: A memory device includes a plurality of planes of memory arrays, each memory array including a plurality of memory cells. The memory device also includes a plurality of word lines and bit lines coupled to the memory cells in each plane, and at least one transistor to select at least one of the memory arrays.

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

Abstract: A steering device for steering front wheels of a four-wheeled vehicle is disclosed, comprising a steering wheel, a steering column, a lower column, and a steering gear box. The lower column is coupled via universal joints to the steering column and the steering gear box. The steering gear box includes a housing in which a rack and a screw rod are accommodated. The rack has an end coupled via a spherical joint to a tie rod, which is jointed to the front wheel. The spherical joint includes an anti-loosening washer. The housing has an inside surface forming a step over which a sleeve is fit for being engageable with the anti-loosening washer of the spherical joint to form a constraint to an inward travel of the spherical joint of the tie rod into the housing so as to set a constraint to steering angle of the front wheel.

Abstract: A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.