Patents by Inventor An-Hsiu Lee

An-Hsiu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8378382
    Abstract: A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: February 19, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chao-I Wu, Ming Hsiu Lee
  • Patent number: 8374019
    Abstract: A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: February 12, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chao-I Wu, Yen-Hao Shih, Ming-Hsiu Lee
  • Publication number: 20130026516
    Abstract: A light-emitting diode (LED) package structure and a packaging method thereof are provided. The packaging method includes: forming first conductive layers on a silicon substrate, and forming a reflection cavity and electrode via holes from a top surface of the silicon substrate; forming a reflection layer on predetermined areas of a surface of the reflection cavity, and forming second conductive layers and metal layers on surfaces of the electrode via holes; and mounting a chip and forming an encapsulant, so as to fabricate the LED package structure. In the present invention, there is no need to perform at least two plating processes for connecting upper and lower conductive layers of the silicon substrate in the electrode via holes, and the problem of poor connection of the conductive layers in the electrode via holes can be avoided, thereby making the fabrication processes simplified and time-effective and also improving the overall production yield.
    Type: Application
    Filed: September 1, 2011
    Publication date: January 31, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Jih-Fu Wang, Chien-Ping Huang, Wen-Hao Lee, Hsien-Wen Chen, Ming-Hsiu Lee
  • Patent number: 8363463
    Abstract: A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: January 29, 2013
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Yen-Hao Shih, Huai-Yu Cheng, Chieh-Fang Chen, Chao-I Wu, Ming Hsiu Lee, Hsiang-Lan Lung, Matthew J. Breitwisch, Simone Raoux, Chung H Lam
  • Patent number: 8350316
    Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: January 8, 2013
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Chung Hon Lam, Ming-Hsiu Lee, Bipin Rajendran
  • Publication number: 20120327708
    Abstract: Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change memory cell. The higher current repair operation can provide a sufficient amount of energy to reverse compositional changes in the phase change material which can occur after repeated set and reset operations. By reversing these compositional changes, the techniques described herein can recover a memory cell which experienced a set or reset failure, thereby extending the endurance of the memory cell. In doing so, phase change based memory devices and methods for operating such devices are provided which have high cycle endurance.
    Type: Application
    Filed: May 15, 2012
    Publication date: December 27, 2012
    Applicants: International Business Machines Corporation, Macronix International Co., Ltd.
    Inventors: Pei-Ying DU, Chao-I Wu, Ming-Hsiu Lee, Sangbum Kim, Chung Hon Lam
  • Publication number: 20120320669
    Abstract: A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 20, 2012
    Applicant: MACROMIX INTERNATIONAL CO., LTD.
    Inventors: MING-HSIU LEE, CHIEH-FANG CHEN
  • Patent number: 8324605
    Abstract: A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: December 4, 2012
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Hsiang-Lan Lung, Chieh-Fang Chen, Yen-Hao Shih, Ming-Hsiu Lee, Matthew J. Breitwisch, Chung Hon Lam, Frieder H. Baumann, Philip Flaitz, Simone Raoux
  • Publication number: 20120274809
    Abstract: A luminance adjusting method of an electronic device is disclosed. The electronic device includes a light sensor, a control module, a memory and a light source module. The memory stores predetermined ambient luminance-light source luminance corresponding information. The luminance adjusting method includes following steps: obtaining an ambient luminance value by sensing ambient light via the light sensor; receiving an inputted adjusting value; adjusting the predetermined ambient luminance-light source luminance corresponding information according to the inputted adjusting value to generate first personalized ambient luminance-light source luminance corresponding information; generating an optimal luminance adjusting value by referring to the first personalized ambient luminance-light source luminance corresponding information and the ambient luminance value; and adjusting the luminance of the light source module according to the optimal luminance adjusting value.
    Type: Application
    Filed: April 27, 2012
    Publication date: November 1, 2012
    Inventors: Chia-Hsin YANG, Yi-Hsiu Lee, Yang-Po Chiu
  • Publication number: 20120243720
    Abstract: A novel auto-play audible publication, which enables to play the contents and voice simultaneously without external players; the audible publication is either of book, newspaper, magazine, booklet, leaflet, calendar, card, CD album, notebook, religious scripture/journal; in particular, the audible publication comprises: thin speaker, play panel, control circuit board, speaker driving flexible circuit board and power supply, of which the control circuit board is provided with a memory for storing all audio data in the audible publication; the play panel can be controlled to select the contents and send signals to the control circuit board, and make the speaker driving flexible circuit board output audio effect to the thin speaker for play back. While simultaneous reading and listening, the audible publication also allows learning acoustically the contents and listen to correct voice for a better learning effect.
    Type: Application
    Filed: March 27, 2011
    Publication date: September 27, 2012
    Inventors: An-Hsiu Lee, Mei-Huei Chiang
  • Publication number: 20120231613
    Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
    Type: Application
    Filed: May 21, 2012
    Publication date: September 13, 2012
    Applicant: Macronix International Co., Ltd.
    Inventors: HSIANG-LAN LUNG, YEN-HAO SHIH, ERH-KUN LAI, MING HSIU LEE, HANG-TING LUE
  • Patent number: 8241928
    Abstract: A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: August 14, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Chao-I Wu, Ming-Chang Kuo
  • Patent number: 8238149
    Abstract: Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 7, 2012
    Assignees: Macronix International Co., Ltd., International Business Machines Corporation
    Inventors: Yen-Hao Shih, Ming-Hsiu Lee, Chao-I Wu, Hsiang-Lan Lung, Chung Hon Lam, Roger Cheek, Matthew J. Breitwisch, Bipin Rajendran
  • Publication number: 20120188813
    Abstract: Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.
    Type: Application
    Filed: August 18, 2011
    Publication date: July 26, 2012
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chih Chien, Ming-Hsiu Lee, Yan-Ru Chen
  • Publication number: 20120187362
    Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
    Type: Application
    Filed: March 30, 2012
    Publication date: July 26, 2012
    Applicant: Macronix International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Chieh-Fang Chen
  • Publication number: 20120170359
    Abstract: A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 5, 2012
    Applicant: Macronix International Co., Ltd.
    Inventors: Chao-I Wu, Yen-Hao Shih, Ming-Hsiu Lee
  • Publication number: 20120161410
    Abstract: A steering apparatus includes a first joint disposed on a control rod that extends rotatably through a head tube, two second joints disposed respectively on two suspension units, and two connecting bars each connected between the first joint and a respective one of the second joints. The first joint includes a seat disposed fixedly on the control rod, at least one first rotating member having a central axis and rotatable on the seat about the central axis of the first rotating member, and at least one second rotating member having a central axis and rotatable on the first rotating member about the central axis of the second rotating member. The axes of the first and second rotating members of the first joint are perpendicular to each other.
    Type: Application
    Filed: June 30, 2011
    Publication date: June 28, 2012
    Inventors: Hsin-Chih Ting, Yen-Hsiu Lee, Chun-Hao Huang
  • Patent number: 8203187
    Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: June 19, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsiang-Lan Lung, Yen-Hao Shih, Erh-Kun Lai, Ming Hsiu Lee, Hang-Ting Lue
  • Patent number: 8198619
    Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: June 12, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming-Hsiu Lee, Chieh-Fang Chen
  • Publication number: 20120138351
    Abstract: The circuit board includes a base board and a pad array mounted on the base board. The pad array includes a plurality of spaced first pads, two second pads, and two third pads. The first pads, the second pads, and the third pads are all parallel to each other. The third pads are between the first pads and the second pads. The first pads electronically and physically connect to an electric element. The second pads and third pads physically connect to the electric element.
    Type: Application
    Filed: April 1, 2011
    Publication date: June 7, 2012
    Applicant: CHI MEI COMMUNICATION SYSTEMS, INC.
    Inventor: I-HSIU LEE