Abstract: Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided.

Abstract: The invention describes a semiconductor cell including a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region.

Abstract: A multifunction printer (MFP) and a stopper applied therein are provided. The MFP includes a body, a top cover and the stopper. The body has a paper conveyor path, a paper holder located in front of an entrance of the paper conveyor path and a first rotating axle located in the paper conveyor path. A first side of the top cover rotates about the first rotating axle to be close to the paper holder. The stopper has a second rotating axle connected to the body, a connecting portion and an eccentric portion. The connecting portion is connected between the second rotating axle and the eccentric portion. The eccentric portion hangs down at the entrance of the paper conveyor path. A center of gravity of the stopper is located in the eccentric portion. A first stopping point of the top cover is located in a rotating path of the eccentric portion.

Abstract: An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.

Abstract: A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte.

Abstract: An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

Abstract: A resistive memory and a fabricating method thereof are provided. The resistive memory includes first and second electrodes, a variable resistance material layer, a first dielectric layer, and a second dielectric layer. The first electrode includes a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer includes a sidewall and first and second surfaces opposite to each other, wherein the first surface is connected with the first portion of the first electrode and the second surface is electrically connected with the second electrode. The second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion. The first dielectric layer is disposed between the first and the second electrodes. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode.

Abstract: A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.

Abstract: A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.

Abstract: A transmission particularly for bicycles, which is capable of multi-speed gear-shifting by means of reverse rotation and comprises: a transmission axle rotatable in both positive and reverse directions, a speed-changing gear set, a speed-changing cam set, and a transmission seat. The speed-changing gear set comprises a plurality of transmission gears and speed-changing gears which are respectively engaging with the transmission gears. When the transmission axle rotates reversely, the speed-changing cam set can be driven in order to control and decide which transmission gear of the speed-changing gear set is to be engaged and driven by the transmission axle during positive rotation, so as to achieve the feature of multi-speed gear-shifting by means of reverse rotation.

Abstract: A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.

Abstract: A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.

Abstract: The present disclosure relates to a silicone resin composition comprising a silicone resin having at least one terminal hydrogen group, a metal alkoxide having at least one C1-6 ailcoxy group, and a silane having at least one terminal vinyl group and at least one terminal C1-6 alkoxy or hydroxyl group. The composition cured has a refractive index greater than 1.4. The present disclosure also relates to an optoelectronic device, which is encapsulated with the aforementioned composition.

Abstract: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

Abstract: A multifunction printer (MFP) and a stopper applied therein are provided. The MFP includes a body, a top cover and the stopper. The body has a paper conveyor path, a paper holder located in front of an entrance of the paper conveyor path and a first rotating axle located in the paper conveyor path. A first side of the top cover rotates about the first rotating axle to be close to the paper holder. The stopper has a second rotating axle connected to the body, a connecting portion and an eccentric portion. The connecting portion is connected between the second rotating axle and the eccentric portion. The eccentric portion hangs down at the entrance of the paper conveyor path. A center of gravity of the stopper is located in the eccentric portion. A first stopping point of the top cover is located in a rotating path of the eccentric portion.

Abstract: A multi-function peripheral (MFP) suited for printing/scanning a paper or a business card is provided. The MFP includes a body and a printing/scanning unit, a feeding roller, and a plurality of idle rollers disposed in the body. The body has a feeding path that the printing/scanning unit, the feeding roller, and the idle rollers are located thereon. The printing/scanning unit used for printing/scanning the paper or the business card on the feeding path. The idle rollers lean against the feeding roller respectively. A path length between two leaning points of any two adjacent idle rollers contacting the feeding roller is shorter than a size of the business card.

Abstract: A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract: A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.

Abstract: A steering apparatus includes a first joint disposed on a control rod that extends rotatably through a head tube, two second joints disposed respectively on two suspension units, and two connecting bars each connected between the first joint and a respective one of the second joints. The first joint includes a seat disposed fixedly on the control rod, at least one first rotating member having a central axis and rotatable on the seat about the central axis of the first rotating member, and at least one second rotating member having a central axis and rotatable on the first rotating member about the central axis of the second rotating member. The axes of the first and second rotating members of the first joint are perpendicular to each other.