Patents by Inventor An Hsu

An Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240164051
    Abstract: A fan module is adapted to be disposed on a mainboard. The fan module includes a base, a stator unit, a circuit board, a first restriction structure and a second restriction structure. The base includes a mounting shaft and a base opening, wherein the mounting shaft has an axis. The mounting shaft is telescoped in the stator unit. The circuit board is coupled to the stator unit, wherein the circuit board includes a circuit board connection port. The first restriction structure restricts the circuit board, wherein the first restriction structure is arranged on the first straight line, and the first restriction structure is disposed a first distance away from the axis. The second restriction structure restricts the circuit board, wherein the second restriction structure is arranged on the second straight line, the second restriction structure is disposed a second distance away from the axis.
    Type: Application
    Filed: June 12, 2023
    Publication date: May 16, 2024
    Inventors: Kuo-Tung HSU, Wen-Chun HSU, Chao-Fu YANG, Shuo-Sheng HSU
  • Publication number: 20240163062
    Abstract: Methods, apparatuses, and computer-readable medium are provided for rate matching. An example method may include receiving a rate matching pattern configuration indicating at least a first control resource set (CORESET) in a first bandwidth part (BWP) and a second CORESET in a second BWP. The example method may also include receiving a physical downlink shared channel (PDSCH) in the first BWP. The example method may include processing the PDSCH transmission based on the rate matching pattern configuration, where the processing may include rate matching around resources of the first CORESET and first associated search space (SS) sets and the second CORESET and second associated SS sets.
    Type: Application
    Filed: May 17, 2022
    Publication date: May 16, 2024
    Inventors: Kazuki TAKEDA, Peter GAAL, Hobin KIM, Andrew CHEN, Chun-Hao HSU, Huilin XU, Harinath Reddy PATEL, Pankaj Shivcharan GUPTA, Ashutosh GUPTA, Neeraj PANWAR
  • Publication number: 20240163785
    Abstract: A method for performing wireless communication in MLO architecture is applicable to an AP MLD connected with a non-AP MLD through multiple links. The multiple links include at least a first link and a second link, the non-AP MLD operates in ML-SMPS mode. The method includes transmitting an initial control frame to the non-AP MLD via the first link, to trigger at least one link of the multiple links to be activated at the non-AP MLD to support a reception with respective negotiated number of spatial streams, receiving a response frame via the first link in response to the transmission of the initial control frame, and initiating frame exchange between the AP MLD and the non-AP MLD via a target link of the at least one link. The target link is selected from the at least one link according to the response frame. The first link is a primary link.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 16, 2024
    Applicant: MEDIATEK INC.
    Inventors: Hao-Hua Kang, Cheng-Ying Wu, Chien-Fang Hsu, Chih-Chun Kuo
  • Publication number: 20240162182
    Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 16, 2024
    Inventors: Yikang Deng, Taegui Kim, Yifan Kao, Jun Chung Hsu
  • Publication number: 20240163072
    Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.
    Type: Application
    Filed: February 2, 2023
    Publication date: May 16, 2024
    Inventors: YU-CHIEH HSU, LING-WEI KE, CHUN-YU CHEN, HONG-YUN WEI
  • Publication number: 20240162833
    Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
  • Publication number: 20240163075
    Abstract: The present disclosure provides a privacy computing method based on homomorphic encryption, which includes steps as follows. The ciphertext data is received, where the ciphertext data has a floating-point homomorphic encryption data structure, and the floating-point homomorphic encryption data structure of the ciphertext data includes the ciphertext mantissa, exponent parameter and gain parameter. The gain parameter sets the precision of the floating point corresponding to the ciphertext mantissa. The exponent parameter is adapted to multiplication or division. The artificial intelligence model performs operations on the ciphertext data to return the ciphertext result.
    Type: Application
    Filed: February 17, 2023
    Publication date: May 16, 2024
    Inventors: Yu Te KU, Chih-Fan HSU, Wei-Chao CHEN, Feng-Hao LIU, Ming-Ching CHANG
  • Publication number: 20240162359
    Abstract: A backsheet of a solar cell module including a substrate, a first protection layer, and a second protection layer is provided. The substrate includes a first surface and a second surface opposite to each other. The first protection layer is disposed on the first surface of the substrate. The second protection layer is disposed on the second surface of the substrate, wherein the first protection layer and the second protection layer include a silicone layer. At least one of the first protection layer and the second protection layer includes diffusion particles, wherein the diffusion particles include zinc oxide, titanium dioxide modified with silicon dioxide, or a combination thereof. A thickness of the first protection layer and a thickness of the second protection layer are respectively 10 ?m to 30 ?m. A solar cell module including the backsheet is also provided.
    Type: Application
    Filed: January 9, 2023
    Publication date: May 16, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Kang Peng, Cheng-Hsuan Lin, Yu-Ling Hsu, Chun-Chen Chiang
  • Publication number: 20240161347
    Abstract: In implementations of image-based searches for templates, a computing device implements a search system to generate an embedding vector that represents an input digital image using a machine learning model. The search system identifies templates that include a candidate digital image to be replaced by the input digital image based on distances between embedding vector representations of the templates and the embedding vector that represents the input digital image. A template of the templates is determined based on a distance between an embedding vector representation of the candidate digital image included in the template and the embedding vector that represents the input digital image. The search system generates an output digital image for display in a user interface that depicts the template with the candidate digital image replaced by the input digital image.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Applicant: Adobe Inc.
    Inventors: Brian Eriksson, Wei-ting Hsu, Santiago Pombo, Sandilya Bhamidipati, Rida Khan, Ravali Devarapalli, Maya Christmas Davis, Lam Wing Chan, Konstantin Blank, Jason Omid Kafil, Di Ni
  • Publication number: 20240157190
    Abstract: An exercise device is providing, including: a frame, including a weighting seat, two first movable pulley assemblies and two second movable pulley assemblies; a first operation assembly, disposed on the frame, including two first connecting members connected to opposing ends of the first cable and a first cable curving back around the two first movable pulley assemblies and the weighting seat; a second operation assembly, including two second connecting members and two second cables each being connected to the frame and curving back around one first movable pulley assembly and one second movable pulley assembly, each second connecting members being connected to one second cable; a third operation assembly, including two third connecting members and two third cables each being connected to the frame and curving back around one second movable pulley assembly, each third connecting members being connected to one third cable.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 16, 2024
    Inventor: YOU-HSIANG HSU
  • Publication number: 20240161457
    Abstract: A computer-implemented method can include: visually presenting visual stimuli to participants in multiple runs, wherein the visual stimuli include pairs of images, each pair including a reference product image and a competitor product image; performing multiple scans on the participants during passive viewing of the visual presenting, the scans including functional magnetic resonance imaging (fMRI); and determining a similarity index based on results of the scans, the similarity index indicating a level a perceived similarity between the reference product image and the competitor product image.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 16, 2024
    Inventors: Ming Hsu, Andrew Stewart Kayser, Zhihao Zhang
  • Publication number: 20240162313
    Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Chun-Liang Hou, Wen-Jung Liao, Chun-Ming Chang, Yi-Shan Hsu, Ruey-Chyr Lee
  • Publication number: 20240162809
    Abstract: A power supply circuit is provided. The power factor correction (PFC) circuit is used to perform a power factor correction according to a first voltage to generate an intermediate voltage. The first storage capacitor is used to store a first electrical energy related to the intermediate voltage. The boost conversion circuit is connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage. The boost conversion circuit includes a first post-stage inductor, a first post-stage diode and a first post-stage transistor. The second storage capacitor is used to store a second electrical energy related to the output voltage. The capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor; the first electrical energy is completely or partially transferred as the second electrical energy.
    Type: Application
    Filed: March 6, 2023
    Publication date: May 16, 2024
    Inventors: Yu-Cheng LIN, Te-Hung YU, Chia-Hui LIANG, Min-Hao HSU
  • Publication number: 20240158459
    Abstract: Provided herein are methods of increasing T-cell function and T-cells produced by these methods. Also provided herein are methods of treating a subject using T-cells produced by these methods.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Applicant: Kyverna Therapeutics, Inc.
    Inventors: John Lee, Erin O’Brien, Jordan Tsai, Lih-Yun Hsu, Faye Wu
  • Publication number: 20240159976
    Abstract: An alignment structure of an optical element includes an optical fiber having a parallel fiber segment and a plurality of bare fiber segments, a cover plate provided with a plurality of side-by-side guide grooves and a plurality of first coupling parts, the bare fiber segments of the optical fiber being arranged in the corresponding guide grooves, cross-sectional shapes of the guide grooves being at least one of U-shaped or V-shaped, and a silicon chip provided with lines and a plurality of second coupling parts. When the cover plate is matched with the silicon chip, the first coupling parts and the second coupling parts are coupled and positioned with each other respectively, and the optical fiber is fixed between the silicon chip and the cover plate.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Inventors: Ting-Ta Hu, Hsu-Liang Hsiao, Po-Yi Wu
  • Publication number: 20240162169
    Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: December 12, 2023
    Publication date: May 16, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yu-Lung Huang, Chee-Key Chung, Yuan-Hung Hsu, Chi-Jen Chen
  • Publication number: 20240160252
    Abstract: A hinge includes a stationary seat and two rotating units. Each rotating unit includes a linkage module that has an extension body that has a arcuate slide rail, a rotating bracket module that is rotatable and that has a fixing pin, and a sliding module that includes a connecting frame, a positioning pin, and a linkage member. The connecting frame has a curved groove that engages the arcuate slide rail such that movement of the rotating units between an opened and a closed state results in movement between the arcuate slide rail and the curved groove. The linkage member has a through hole, and an elongated slot which the fixing pin passes through to connect the rotating bracket module such that movement of the rotating units between the opened and closed states results in movement between the fixing pin and the elongated slot.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 16, 2024
    Applicant: FOSITEK CORPORATION
    Inventors: An-Szu HSU, An-Wei CHUNG
  • Publication number: 20240161957
    Abstract: Provided is an inductor structure and manufacturing method thereof, including forming an inductance coil in a semiconductor packaging carrier plate and disposing a patterned magnetic conductive layer in the inductance coil. Therefore, a patterned build-up wiring method is used to form a magnetic material in the carrier plate, thereby improving electrical characteristics of the inductor.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 16, 2024
    Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung CHOU, Shih-Ping HSU, Chu-Chin HU
  • Publication number: 20240160828
    Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
  • Publication number: 20240161505
    Abstract: Provided is behavior image sensor system, including a first image capturing unit and a control unit. The first image capturing unit is used for capturing a moving image. The control unit is electrically connected to the first image capturing unit, receives the moving image, and calculates a moving track of a moving object in the moving image, thereby determining whether the moving track of the moving object conforms to a particularly dangerous behavior pattern. As such, the behavior image sensor system does not need to capture a static image of a static object completely and determine a behavior pattern of the static object, so that the behavior image sensor system may reduce the quantity of data a lot and is suitable for all kinds of environment.
    Type: Application
    Filed: August 9, 2023
    Publication date: May 16, 2024
    Inventors: Hsu-Wen Fu, Jun-Wen Chung, Chia-Hao Chang