Patents by Inventor An Hsu

An Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240193958
    Abstract: A processing method for vehicle surround view, a vehicle surround view system and an in-vehicle processing device are provided. The processing method for vehicle surround view includes the following steps: obtaining a first exterior image and a second exterior image; recognizing a first interest object in the first exterior image and a second interest object in the second exterior image; fitting the first interest object to a first geometric contour and fitting the second interest object to a second geometric contour; applying the first geometric contour and the second geometric contour on a 3D model, to obtain a ground point, a first contour position and a second contour position; obtaining a merged contour position according to the ground point; and projecting the first interest object or the second interest object at the merged contour position on a vehicle surround image.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 13, 2024
    Inventors: Yen-Chun CHEN, Jiun-Shiung Chen, Chien-Chung Lee, Chi-Min Weng, Chuen-Ning Hsu
  • Publication number: 20240190596
    Abstract: In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.
    Type: Application
    Filed: November 18, 2023
    Publication date: June 13, 2024
    Inventors: Tsung-Sheng KUO, Hsu-Shui LIU, Jiun-Rong PAI, Yang-Ann CHU, Chieh-Chun LIN, Shine CHEN
  • Publication number: 20240192581
    Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a patterned absorber layer on the reflective multilayer stack is provided. The patterned absorber layer includes an alloy comprising tantalum and at least one alloying element. The at least one alloying element includes at least one transition metal element or at least one Group 14 element.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 13, 2024
    Inventors: Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
  • Publication number: 20240190139
    Abstract: Provided is a printing system with intelligent color-matching, including a storage device, a printing device, and a processing device. The storage device stores a program, a color-matching dataset, and a color-matching model. The color-matching dataset contains multiple pieces of color-matching data, and each piece of color-matching data includes an ink formula and a corresponding printing color value for the ink formula. The printing device is controlled to produce printed products. The processing device loads the program from the storage device to perform the following tasks: training the color-matching model using the color-matching dataset; inputting the expected color value into the trained color-matching model, and obtaining a predicted formula output by the trained color-matching model; and based on the predicted formula, controlling the printing device to produce the printed product.
    Type: Application
    Filed: December 8, 2023
    Publication date: June 13, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsi-Kang SHIH, Wesley Jen-Yang CHANG, Mei-Wen HSU, Wen-Pin CHUANG, Shinn-Jen CHANG
  • Publication number: 20240192597
    Abstract: A polymer is formed by a reaction of phenolic epoxy resin or bisphenol epoxy resin and carboxylic acid, wherein the phenolic epoxy resin has a chemical structure of wherein W is H, alkyl group, or halogen. R1 is methylene, methylene diphenyl, dimethylene benzene, tetrahydrodicyclopentadiene, or n=1 to 8. The bisphenol epoxy resin has a chemical structure of wherein Z is H or alkyl group; R4 is methylene, methylmethylene, dimethylmethylene, ethylmethylmethylene, bi(trifluoromethyl)methylene, fluorenylidene, or sulfonyl group; and p=1 to 10. The carboxylic acid has a chemical structure of HOOC—Ar—(—X)m, HOOC—R2, or a combination thereof, wherein Ar is benzene or naphthalene; X is hydroxy group, alkoxy group, or alkyl group, and at least one X is hydroxy group; m=1 to 3, wherein R2 is C3-7 alkyl group.
    Type: Application
    Filed: October 25, 2023
    Publication date: June 13, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Ying HSU, Yao-Jheng HUANG, Ming-Tzung WU, Chin-Hua CHANG, Te-Yi CHANG
  • Publication number: 20240190186
    Abstract: A system for setting tire sensor identification code includes a tire sensor, a database and a handheld device. The tire sensor includes an identification code. The database stores vehicle data associated with a code learning method of the identification code of the tire sensor. When the vehicle data is inputted, a link pattern associated with a specific vehicle and a code learning flow of a vehicle computer of the vehicle is generated. The handheld device includes a memory and a link pattern capture module. A plurality of communication protocols are stored in the memory. When the link pattern is captured by the link pattern capture module, one of the communication protocols is selected from the memory and is burned to the tire sensor.
    Type: Application
    Filed: August 4, 2023
    Publication date: June 13, 2024
    Inventor: CHIN -YAO HSU
  • Publication number: 20240192692
    Abstract: A heading and attitude correction method and a heading and attitude correction system are provided. The method includes: obtaining attitude data in a period of time; performing a linear regression analysis on the attitude data and time points in the time period to obtain a regression line and a standard deviation; obtaining a deviation value between the attitude data and the regression line at each of the time points; excluding the attitude data for which the deviation value is greater than or equal to at least twice the standard deviation; grouping the attitude data according to a grouping value to form clusters; comparing a total quantity of the attitude data in each of the clusters, and defining one of the clusters with a largest total quantity as an ideal cluster; and calculating an average of the attitude data in the ideal cluster as a reasonable attitude data.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 13, 2024
    Inventors: YUNG-TAI HSU, CHUN-HENG CHAO, YEN-WEI WANG, BO-YU ZHU
  • Publication number: 20240195083
    Abstract: An antenna module including a first radiator and a second radiator is provided. The first radiator includes a first segment to a fifth segment connected in sequence. A first slot is formed between the second segment and the fourth segment. The second radiator has an edge. A first retracting distance is between the second segment and an extension line. A second retracting distance is between the fourth segment and the extension line. The first segment resonates at a first high frequency band. The first radiator and the first slot resonate at a low frequency band and a second high frequency band. The first retracting distance, the second retracting distance, the second segment, the fourth segment, the fifth segment and the first slot resonate at a third high frequency band. The first segment and the second radiator resonate at a fourth high frequency band. In addition, an electronic device is provided.
    Type: Application
    Filed: October 17, 2023
    Publication date: June 13, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Shih-Keng Huang, Hau Yuen Tan, Chih-Wei Liao, Chia-Hung Chen, Wen-Hgin Chuang, Chia-Hong Chen, Lin-Hsu Chiang, Hsi Yung Chen
  • Publication number: 20240193970
    Abstract: An authentication processing system includes a memory storing a portrait fraud detection application, and a processing unit coupled with the memory and configured to execute the portrait fraud detection application. The portrait fraud detection application, when executed, configures the processing unit to receive a capture of a document including a portrait photo and at least one overlay, detect a face in the portrait photo among the at least one overlay in the capture, and determine the portrait photo is fraudulent; and initiate an indication the document is fraudulent.
    Type: Application
    Filed: December 7, 2022
    Publication date: June 13, 2024
    Inventors: Rein-Lien Hsu, Brian Martin
  • Publication number: 20240195047
    Abstract: The invention discloses a semiconductor package antenna structure and its manufacturing method, wherein the semiconductor package antenna structure includes a first substrate, a semiconductor chip, and a second substrate. The first substrate has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer. The semiconductor chip is embedded in the first substrate and coupled to the first redistribution layers. The second substrate has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer is protruded from the second redistribution layer. The second substrate is connected to the first substrate by a second conductive pillar layer, and the air dielectric layer is located between the second redistribution layer, the second conductive pillar layer, and the first substrate.
    Type: Application
    Filed: November 27, 2023
    Publication date: June 13, 2024
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Publication number: 20240194593
    Abstract: A method of forming a semiconductor device includes the following operations. A substrate is provided with an electric component. A composite dielectric layer is formed on the substrate and covers the electric component. An opening is formed through the composite dielectric layer. A directional etching process is performed to widen an upper portion of the opening. A metal feature is formed in the opening.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Su, Yung-Hsu Wu, Hsin-Ping Chen, Chih Wei LU, Wei-Hao Liao, Hsi-Wen Tien, Cherng-Shiaw Tsai
  • Publication number: 20240194678
    Abstract: A method includes depositing an epitaxial stack over a substrate, the epitaxial stack comprising alternating first semiconductor layers and second semiconductor layers, wherein the first semiconductor layers comprise a different semiconductor composition from that of the second semiconductor layers; forming a dielectric wall in the epitaxial stack; removing a first subset of the first semiconductor layers on a first side of the dielectric wall, while leaving a first subset of the second semiconductor layers on the first side of the dielectric wall; removing a second subset of the second semiconductor layers on a second side of the dielectric wall, while leaving a second subset of the first semiconductor layers on the second side of the dielectric wall; forming a first gate structure around the first subset of the second semiconductor layers; and forming a second gate structure around the second subset of the first semiconductor layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: June 13, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chih HOU, Chun-Jun LIN, Feng-Ming CHANG, Shu-Ning HSU
  • Publication number: 20240194738
    Abstract: A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.
    Type: Application
    Filed: February 27, 2024
    Publication date: June 13, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Publication number: 20240195048
    Abstract: A near field communication (NFC) antenna includes a carrier having a disk including a first surface and a second surface. The disk surrounds a central bore. The central bore is open through the disk between a top of the carrier and a bottom of the carrier. The NFC antenna includes an antenna circuit on the disk. The antenna circuit includes a first pad and a second pad electrically connected to the first pad. The NFC antenna includes an electronic component at the first surface of the disk and coupled to the first pad. The NFC antenna includes an antenna element coupled to the second surface of the disk. The antenna element includes a conductor arranged as an RF coil. The RF coil extends along the disk and surrounds the central bore. An end of the RF coil is coupled to the second pad.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 13, 2024
    Inventors: Jung-Hoon Kim, Kuei Hsu Hsiang, Hoo Shin, Kiran Vanjani, Chang Hyun Lee
  • Publication number: 20240194764
    Abstract: A semiconductor device includes semiconductor channel members disposed over a substrate, a gate dielectric layer disposed on and wrapping around the semiconductor channel members, a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor channel members, a source/drain (S/D) epitaxial layer in physical contact with the semiconductor channel members, and a dielectric spacer interposing the S/D epitaxial layer and the gate dielectric layer. The dielectric spacer includes a first dielectric layer in physical contact with the gate dielectric layer and a second dielectric layer in physical contact with the first dielectric layer. The first dielectric layer has a dielectric constant higher than that of the second dielectric layer. The second dielectric layer separates the first dielectric layer from physically contacting the S/D epitaxial layer.
    Type: Application
    Filed: February 19, 2024
    Publication date: June 13, 2024
    Inventors: Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh, Kuan-Lun Cheng, Chung-Wei Wu, Zhiqiang Wu
  • Publication number: 20240194386
    Abstract: An inductor structure is provided, in which an inductance coil in the shape of a toroidal coil or a helical coil is arranged in an insulator, and a magnetically permeable body made of a magnetically permeable material is a multi-layer stacked structure and arranged in the inductance coil, where the magnetically permeable body is free from being electrically connected to the inductance coil. Therefore, the magnetically permeable body made of a magnetically permeable material in the form of a multi-layer stacked structure may effectively improve the electrical characteristics of the inductor structure.
    Type: Application
    Filed: December 8, 2023
    Publication date: June 13, 2024
    Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Shih-Ping HSU, Pao-Hung CHOU
  • Publication number: 20240194794
    Abstract: Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.
    Type: Application
    Filed: January 18, 2024
    Publication date: June 13, 2024
    Inventors: CHIA-MING HSU, YI-JING LI, CHIH-HSIN KO, KUANG-HSIN CHEN, DA-WEN LIN, CLEMENT HSINGJEN WANN
  • Publication number: 20240194619
    Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.
    Type: Application
    Filed: February 18, 2024
    Publication date: June 13, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan
  • Publication number: 20240194650
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.
    Type: Application
    Filed: February 26, 2024
    Publication date: June 13, 2024
    Inventors: Chin-Min Lin, Hung-Jen Hsu, Dun-Nian Yaung
  • Publication number: 20240194646
    Abstract: A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.
    Type: Application
    Filed: September 29, 2023
    Publication date: June 13, 2024
    Inventors: Chin-Tang Hsieh, Lung-Hua Ho, Chih-Ming Kuo, Chen-Yu Wang, Chih-Hao Chiang, Pai-Sheng Cheng, Kung-An Lin, Chun-Ting Kuo, Yu-Hui Hu, Wen-Cheng Hsu