Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, a second encapsulant and a first RDL structure. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die. The first RDL structure is disposed on the bridge die and the second encapsulant.

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a curved bottom surface.

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Abstract: A probe card device and a dual-arm probe are provided. The dual-arm probe has a probe length, and includes a bifurcation end portion and a testing end portion. The dual-arm probe has two broad side surfaces respectively arranged on two opposite sides thereof The dual-arm probe has a separation slot that is recessed from a bifurcation opening of the bifurcation end portion toward the testing end portion and that penetrates from one of the two broad side surfaces to the other one, so that two branch arms of the dual-arm probe are defined by the separation slot and are spaced apart from each other. The separation slot has a slot length being 50% to 90% of the probe length. In a cross section of the two branch arms, an area of any one of the two branch arms is 90% to 110% of that of the other one.

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Abstract: A probe card device and a self-aligned probe are provided. The self-aligned probe includes a fixing end portion configured to be abutted against a space transformer, a testing end portion configured to detachably abut against a device under test (DUT), a first connection portion connected to the fixing end portion, a second connection portion connected to the testing end portion, and an arced portion that connects the first connection portion and the second connection portion. The fixing end portion and the testing end portion jointly define a reference line passing there-through. The first connection portion has an aligned protrusion, and a maximum distance between the arced portion and the reference line is greater than 75 ?m and is less than 150 ?m.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A board-like connector, a single-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of single-arm bridges spaced apart from each other and an insulating layer. Each of the single-arm bridges includes a carrier, a cantilever extending from and being coplanar with the carrier, an abutting column, and an abutting end portion, the latter two of which extend from the cantilever and are respectively arranged at two opposite sides of the cantilever. The insulating layer connects the carriers of the single-arm bridges, and the abutting column of each of the single-arm bridges protrudes from the insulating layer. The abutting column and the abutting end portion of each of the single-arm bridges are configured to abut against two boards, respectively.

Abstract: A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.

Abstract: A board-like connector, a dual-ring bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-ring bridges spaced apart from each other and an insulating layer. Each of the dual-ring bridges includes two carrying rings, two cantilevers respectively extending from and being coplanar with the two carrying rings, two abutting columns respectively extending from the two cantilevers along two opposite directions, and a bridging segment that connects the two carrying rings. The insulating layer connects the two carrying rings of the dual-ring bridges, and the two abutting columns of the dual-ring bridges respectively protrude from two opposite sides of the insulating layer. The two abutting columns of each of the dual-ring bridges are configured to be respectively abutted against two boards.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.

Abstract: The semiconductor structure includes a plurality of first dies, a plurality of second dies disposed over each of the first dies, and a dielectric material surrounding the plurality of first dies and the plurality of second die. Each of the second dies overlaps a portion of each first die.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure, a redistribution line, and a seal ring structure. The redistribution line and the seal ring structure are in the dielectric structure, the seal ring structure continuously surrounds the redistribution line, the seal ring structure includes a first seal ring and a second seal ring over and electrically connected to the first seal ring, and the redistribution structure has a first sidewall, a first surface, and a second surface opposite to the first surface. The chip package structure includes a chip structure over the first surface. The chip package structure includes a ground bump over the second surface. The chip package structure includes a conductive shielding film covering the chip structure and the first sidewall of the redistribution structure.

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Abstract: A probe card device and a fence-like probe thereof are provided. The fence-like probe includes a stroke segment, a fan-out segment, and a testing segment. The stroke segment is in an elongated shape defining a longitudinal direction, and the stroke segment has two end portions and a plurality of penetrating slots that are arranged along a fan-out direction perpendicular to the longitudinal direction, so that the stroke segment is deformable to store an elastic force by being applied with a force. The fan-out segment and the testing segment are respectively connected to the two end portions of the stroke segment. The fan-out segment has a fixing point arranged away from the stroke segment, and the testing segment has an abutting point arranged away from the stroke segment. Along the fan-out direction, the fixing point is spaced apart from the abutting point by a fan-out distance.

Abstract: A probe card device and a fence-like probe thereof are provided. The fence-like probe includes a stroke segment, a fan-out segment, and a testing segment. The stroke segment is in an elongated shape defining a longitudinal direction, and the stroke segment has two end portions and a plurality of penetrating slots that are arranged along a fan-out direction perpendicular to the longitudinal direction, so that the stroke segment is deformable to store an elastic force by being applied with a force. The fan-out segment and the testing segment are respectively connected to the two end portions of the stroke segment. The fan-out segment has a fixing point arranged away from the stroke segment, and the testing segment has an abutting point arranged away from the stroke segment. Along the fan-out direction, the fixing point is spaced apart from the abutting point by a fan-out distance.

Abstract: A probe card device and a fan-out probe thereof are provided. The fan-out probe includes a stroke segment, a fan-out segment, and a testing segment. The stroke segment is in a straight shape defining a longitudinal direction, and the stroke segment has two end portions. The stroke segment is bendable when the two end portions are respectively applied with forces along two opposite directions. The fan-out segment and the testing segment are respectively connected to the two end portions of the stroke segment. The fan-out segment has a fixing point arranged away from the stroke segment, and the testing segment has an abutting point arranged away from the stroke segment. Along a fan-out direction perpendicular to the longitudinal direction, the fixing point is spaced apart from the abutting point by a fan-out distance.

Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.