Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plurality of first fins, a first work function layer over the plurality of first fins, and a first contact layer over the first work function layer. The second device includes a plurality of second fins, a second work function layer and the first work function layer over the plurality of the second fins, and a second contact layer over the first work function layer and the second work function layer. A distance between a bottom surface of the first work function layer and a bottom surface of the first contact layer is greater than a distance between a side surface of the first work function layer of the first device and a side surface of the first contact layer.

Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.

Abstract: A semiconductor device according to the present disclosure includes a first conductive feature and a second conductive feature in a first dielectric layer, a buffer layer over the first dielectric layer, a second dielectric layer over the buffer layer, a first bottom via extending through the buffer layer and the second dielectric layer, a second bottom via extending through the buffer layer and the second dielectric layer, a first bottom electrode disposed on the first bottom via, a second bottom electrode disposed on the second bottom via, a first magnetic tunnel junction (MTJ) stack over the first bottom electrode, and a second MTJ stack over the second bottom electrode. The first MTJ stack and the second MTJ stack have a same thickness. The first MTJ stack has a first width and the second MTJ stack has a second width greater than the first width.

Abstract: An information processing method, a device, and a storage medium, which relates to a screen transmission technology, are provided. The method includes: in response to a first operation acting on characters, displaying the characters in an input box, where the input box is an input box of a screen transmission application; determining a target screen-transmission code in candidate screen-transmission codes stored in a screen-transmission sending end according to input characters, where the number of characters contained in the target screen-transmission code is greater than the number of the input characters, the target screen-transmission code contains the input characters, the target screen-transmission code is a screen-transmission code of a screen-transmission receiving end, and the target screen-transmission code is acquired by the screen-transmission sending end from a beacon received from the screen-transmission receiving end; displaying the target screen-transmission code in the input box.

Abstract: A heat sink device, comprising a body, at least a heat pipe, and a base. The body has a first side and a second side onto which a heat source is attached. The heat pipe has a heat-absorbing portion and a heat-dissipating portion. The heat-absorbing portion is attached to the first side, while the heat-dissipating portion is away from the heat-absorbing portion, so that the heat generated by the heat source is absorbed by the heat-absorbing portion and transferred to the distal end of the heat-dissipating portion. The base is disposed on the heat pipe and above the body.

Abstract: Disclosed are a high-temperature superconducting suspension type wireless power transmission device and an assembly method thereof. The device comprises an alternating current power supply, wherein the alternating current power supply is electrically connected with a transmitting coil, and the transmitting coil is made of high-temperature superconducting materials; a suspended matter is mounted above the transmitting coil, the suspended matter is electrically connected with a receiving coil corresponding to the transmitting coil, and a plurality of permanent magnets fixedly connected with the suspended matter are uniformly mounted along the periphery of the receiving coil; and the transmitting coil is located in a low-temperature container to maintain a superconducting state. In combination with the superconducting magnetic suspension technology and the superconducting wireless charging technology, power is stored without the need of a complex energy storage device.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: The present disclosure is at least directed to utilizing air curtain devices to form air curtains to separate and isolate areas in which respective workpieces are stored from a transfer compartment within a workpiece processing apparatus. The transfer compartment of the workpiece processing apparatus includes a robot configured to transfer or transport ones of the workpieces to and from these respective storage areas through the transfer compartment and to and from a tool compartment. A tool is present in the tool compartment for processing and refining the respective workpieces. Clean dry air (CDA) may be circulated through the respective storage areas. The air curtains formed by the air curtain devices and the circulation of CDA through the respective storage areas reduces the likelihood of the generation of defects, damages, and degradation of the workpieces when present within the workpiece processing apparatus.

Abstract: A semiconductor structure is provided. The semiconductor structure includes fin structures, a gate structure across the fin structures, and a dielectric layer. The gate structure includes a work function layer over the gate dielectric layer, and a contact layer over the work function layer. A portion of the work function layer is located between the fin structures, and a top surface of the portion is higher than a top surface of the fin structures. A top surface of the work function layer and a top surface of the dielectric layer are substantially on a same level. A method for forming a semiconductor structure is also provided.

Abstract: A memory device includes a memory unit and a shielding element disposed on the memory unit. The memory unit includes a bottom electrode, a memory element disposed on the bottom electrode, and a top electrode disposed on the memory element. The shielding element is disposed on the memory unit to deviate an external magnetic field away from the memory element.

Abstract: Disclosed are a method and a device for manufacturing liquid hydrogen by offshore off-grid superconducting wind turbine. The method comprises the following steps: electrolyzing seawater to obtain hydrogen based on electric energy output by an offshore off-grid superconducting wind turbine generator, liquefying the hydrogen into prepared liquid hydrogen, and outputting a part of the liquid hydrogen as the refrigerant of the offshore off-grid superconducting wind turbine generator. The device comprises a liquid preparation platform, an offshore off-grid superconducting wind turbine generator, a seawater electrolysis unit, a hydrogen liquefaction unit and a liquid hydrogen storage unit, wherein the power ends of the seawater electrolysis unit and the hydrogen liquefaction unit are connected with the output end of the offshore off-grid superconducting wind turbine generator, and the hydrogen liquefaction unit is connected with the coolant input end of the offshore off-grid superconducting wind turbine generator.

Abstract: The present disclosure provides a semiconductor structure, including a memory region, a logic region adjacent to the memory region, a first magnetic tunneling junction (MTJ) cell and a second MTJ cell over the memory region, and a carbon-based layer over the memory region, wherein the carbon-based layer includes a recess between the first MTJ cell and the second MTJ cell.

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure fills the trench and extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.

Abstract: A detecting method for a behavior disorder event during rapid-eye-movement sleep is provided. The detecting method includes: collecting a heart rate value and a motion value of a user per epoch within a time period; generating a plurality of corresponding sleep condition values by using the motion values, to distinguish epochs into an awake period and a sleep period; transforming the motion values corresponding to the sleep period into a score according to a predetermined rule, to generate a plurality of sleep depth scores, and distinguishing the sleep period into a light sleep period and a deep sleep period by using the sleep depth scores; grouping the heart rate values corresponding to the deep sleep period as a high heart rate group and a low heart rate group; and determining, when the motion values corresponding to the high heart rate group satisfy a condition, that a behavior disorder event happens.

Abstract: A compound as represented by formula I-1, or a pharmaceutically acceptable salt, a stereoisomer, or a solvate thereof are effective in reducing ALT, AST and ALP as well as helpful in treating hepatic pathological injuries (e.g. hepatocyte steatosis). The compound has wide application prospects in the preparation of a drug for preventing and/or treating liver diseases such as fatty liver, hepatic fibrosis and liver cirrhosis.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

Abstract: Some implementations described herein provide techniques and apparatuses for forming a semiconductor device including a metal-insulator-metal capacitor. The metal-insulator-metal capacitor includes a dielectric pad layer having a portion between a capacitor bottom metal electrode layer and a portion of an insulator layer. The dielectric pad layer may preserve a thickness of the insulator layer to reduce a likelihood of a leakage between a capacitor top metal electrode layer and the capacitor bottom metal electrode layer. The dielectric pad layer may also enable a reduction in a thickness of the insulator layer to increase a capacitance of the metal-insulator-metal capacitor.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.