Patents by Inventor An Sun Hyun
An Sun Hyun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7939663Abstract: The present invention relates to a light emitting transition metal compound represented by the Chemical Formula 1 and Chemical Formula 2 and an organic electroluminescence device including the same. In the above Chemical Formulae 1 and 2, M is Ir, Pt, Rh, Re, Os, or the like, m is 2 or 3 and n is 0 or 1, where the sum of m and n is 3, provided that the sum of m and n is 2 when M is Pt, X and Z are the same or different and may be N or P, and Y is O, S, or Se.Type: GrantFiled: January 8, 2007Date of Patent: May 10, 2011Assignees: Samsung Electronics Co., Ltd., Industry-University Cooperation Foundation, Hanyang UniversityInventors: Dong-Hack Suh, Jin-Soo Lim, Ji-Ho Kim, Sun-Hyun Choi
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Patent number: 7868836Abstract: An antenna for a mobile terminal includes a substrate, a dipole placed on the substrate, a loop placed on the substrate, and a matching circuit on the substrate. The matching circuit comprises at least one of a variable capacitor or a variable inductor. The radiation center of the loop substantially coincides with the radiation center of the dipole.Type: GrantFiled: May 10, 2007Date of Patent: January 11, 2011Assignee: LG Electronics Inc.Inventors: Orest Genrihovich Vendik, Ivan Andreevich Pakhomov, An Sun Hyun, Kang Jae Jung, Dong Ho Lee
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Publication number: 20100330789Abstract: A method of forming the gate patterns of a nonvolatile memory device comprises stacking a gate insulating layer and a first conductive layer over a semiconductor substrate; forming isolation hard mask patterns over the first conductive layer; etching the first conductive layer using the isolation hard mask patterns as etch barriers, thus exposing the gate insulating layer; etching the gate insulating layer using the isolation hard mask patterns as etch barriers, thus exposing the semiconductor substrate; after exposing the semiconductor substrate, forming a passivation layer on the sidewalls of the first conductive layers and on the sidewalls of the gate insulating layers; and etching the semiconductor substrate using the passivation layer and the isolation hard mask patterns as etch barriers, thus forming trenches in the semiconductor substrate.Type: ApplicationFiled: June 16, 2010Publication date: December 30, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Chan Sun Hyun
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Patent number: 7759232Abstract: A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate, forming an etch barrier layer and a second insulating layer over the first insulating layer, forming damascene patterns in the second insulating layer, forming a mask layer over the second insulating layer of other region except a region in which the contact plugs are formed so that the damascene patterns are exposed through the region in which the contact plugs are formed, removing the etch barrier layer under the exposed damascene patterns using an etching process employing the mask layer, and removing the mask layer.Type: GrantFiled: December 26, 2008Date of Patent: July 20, 2010Assignee: Hynix Semiconductor Inc.Inventor: Chan Sun Hyun
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Publication number: 20100112964Abstract: The present invention relates to a wrist watch type mobile terminal, and may include a conductive metal housing connected with a band or strap to be worn on a human body, and formed to be operable as an antenna at a specific bandwidth, a wireless communication module configured to process a signal transmitted and/or received by the housing, and a feeding portion configured to electrically connect the metal housing with the wireless communication module. The metal housing thereof may function as an antenna transmitting and/or receiving a specific bandwidth, and thus has an advantage of facilitating the implementation of the wireless performance and improving the appearance thereof, compared to a case in which an antenna is disposed within the housing having a small and limited size.Type: ApplicationFiled: November 3, 2009Publication date: May 6, 2010Inventors: Kyung-Hack YI, Hyun-Jun Kim, Man-Su Shin, An-Sun Hyun
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Patent number: 7696087Abstract: In a method of forming a dual damascene pattern of a semiconductor device, horns that occur while forming a trench constituting the dual damascene pattern are removed in an intermediate process of forming the trench. Thus, the source of particles, which occur due to the horns in a cleaning process performed after the dual damascene pattern is formed, may be removed. Accordingly, an increase of contact resistance due to particles may be prevented, and a reduction in the yield of semiconductor devices may also be improved.Type: GrantFiled: June 28, 2008Date of Patent: April 13, 2010Assignee: Hynix Semiconductor Inc.Inventor: Chan Sun Hyun
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Publication number: 20090326236Abstract: The present invention relates to a light emitting binuclear transition metal compound of Chemical Formulae 1 and 2, and an organic electroluminescence device including the compound. In the Chemical Formulae 1 and 2, M is selected from Ir, Pt, Rh, Re, and Os, and m is 2, provided that the m is 1 when M is Pt.Type: ApplicationFiled: January 8, 2007Publication date: December 31, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.,Inventors: Dong-Hack Suh, Jin-Soo Lim, Ji-Ho Kim, Sun-Hyun Choi
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Publication number: 20090243944Abstract: A portable terminal is provided that includes a terminal body having a receiver, a ground unit connected to an antenna mounted at the terminal body, and an electric field reducing unit connected to the ground unit and partially transferring a current flowing in the ground unit to a side surface of the terminal body. The strength of the electric field formed at the periphery of the receiver of the portable terminal may be reduced, thus minimizing interference between the portable terminal and the hearing aid.Type: ApplicationFiled: February 27, 2009Publication date: October 1, 2009Inventors: Kang-Jae JUNG, An-Sun Hyun, Chang-Won Yun
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Patent number: 7576011Abstract: A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a second etching stop layer on the first etching stop layer; forming an insulating layer on the second etching stop layer; removing the insulating layer placed between the select lines, the second etching stop layer and the first etching stop layer to form a contact hole through which a portion of the semiconductor substrate is exposed; and filling the contact hole with conductive material to form a contact plug, and so the nitride layer is thinly formed and the high dielectric layer is then formed to form the etching stop layer. Due to the above, a layer stress caused by the nitride layer can be minimized, and it is possible to resolve a problem of exposing the semiconductor substrate caused by a damage of the etching stop layer.Type: GrantFiled: May 11, 2007Date of Patent: August 18, 2009Assignee: Hynix Semiconductor Inc.Inventor: Chan Sun Hyun
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Publication number: 20090186486Abstract: A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate, forming an etch barrier layer and a second insulating layer over the first insulating layer, forming damascene patterns in the second insulating layer, forming a mask layer over the second insulating layer of other region except a region in which the contact plugs are formed so that the damascene patterns are exposed through the region in which the contact plugs are formed, removing the etch barrier layer under the exposed damascene patterns using an etching process employing the mask layer, and removing the mask layer.Type: ApplicationFiled: December 26, 2008Publication date: July 23, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Chan Sun HYUN
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Publication number: 20090163032Abstract: In a method of forming a dual damascene pattern of a semiconductor device, horns that occur while forming a trench constituting the dual damascene pattern are removed in an intermediate process of forming the trench. Thus, the source of particles, which occur due to the horns in a cleaning process performed after the dual damascene pattern is formed, may be removed. Accordingly, an increase of contact resistance due to particles may be prevented, and a reduction in the yield of semiconductor devices may also be improved.Type: ApplicationFiled: June 28, 2008Publication date: June 25, 2009Applicant: Hynix Semiconductor Inc.Inventor: Chan Sun HYUN
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Publication number: 20090096010Abstract: A nonvolatile memory device and a fabrication method thereof are disclosed. The nonvolatile memory device comprises a tunnel insulating film formed on an active region of a semiconductor substrate, a first conductive layer for a floating gate formed on the tunnel insulating film, a dielectric layer formed on the first conductive layer, a second conductive layer for a control gate formed on the dielectric layer, an etch-stop layer formed on the second conductive layer, and a gate electrode layer formed on the etch-stop layer. Accordingly, there is no difference in the degree to which the conductive layer under the gate electrode layer is etched when etching the gate electrode layer of the memory cell region and the peri region.Type: ApplicationFiled: December 24, 2007Publication date: April 16, 2009Applicant: HYNIX SEMICONDUCTORInventor: Chan Sun Hyun
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Publication number: 20090068834Abstract: In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semiconductor substrate. In an etch process of forming the contact plug, the passivation layer formed on sidewalls of the select lines is formed twice to protect the sidewalls of the select lines. Accordingly, the sidewalls of the select lines can be prevented from being damaged. Consequently, a process margin necessary to form a contact plug can be increased and, therefore, a smaller contact plug can be formed.Type: ApplicationFiled: June 27, 2008Publication date: March 12, 2009Applicant: Hynix Semiconductor Inc.Inventor: Chan Sun Hyun
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Patent number: 7498221Abstract: A method of forming a gate of a semiconductor device, including the steps of sequentially forming a tunnel oxide film, a nitride film, a dielectric layer, a polysilicon layer, a metal silicide film, and a hard mask film on a semiconductor substrate; sequentially etching the hard mask film, the metal silicide film, the polysilicon layer, and a predetermined region of the dielectric layer, forming a control gate pattern and also exposing the nitride film; performing a thermal oxidization process on both sides of the control gate pattern, forming an oxide film; and stripping the exposed nitride film by a wet etch process, thereby exposing the tunnel oxide film.Type: GrantFiled: July 20, 2006Date of Patent: March 3, 2009Assignee: Hynix Semiconductor Inc.Inventor: Chan Sun Hyun
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Publication number: 20080275239Abstract: The present invention relates to a light emitting transition metal compound represented by the Chemical Formula 1 and Chemical Formula 2 and an organic electroluminescence device including the same. In the above Chemical Formulae 1 and 2, M is Ir, Pt, Rh, Re, Os, or the like, m is 2 or 3 and n is 0 or 1, where the sum of m and n is 3, provided that the sum of m and n is 2 when M is Pt, X and Z are the same or different and may be N or P, and Y is O, S, or Se.Type: ApplicationFiled: January 8, 2007Publication date: November 6, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.,Inventors: Dong-Hack Suh, Jin-Soo Lim, Ji-Ho Kim, Sun-Hyun Choi
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Publication number: 20080261667Abstract: A mobile terminal is provided that includes a first area having a first conductive surface, a second area having a second conductive surface, the second area separated from the first area, and a feeding point formed between the first conductive surface and the second conductive surface to supply electrical signals to or from the first and the second conductive surfaces.Type: ApplicationFiled: April 17, 2008Publication date: October 23, 2008Inventors: Dong Ho Lee, An-Sun Hyun, SungShin Kong
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Publication number: 20080211037Abstract: A method of forming an isolation layer of a semiconductor device includes the steps of forming a gate insulating layer and a conductive layer on an active area of a semiconductor substrate; forming a spacer layer on side walls of the conductive layer; forming a trench on the semiconductor substrate between the spacer layer-covered side walls; removing the spacer layer to form a step on an upper edge of the trench; and forming a liner insulating layer on the trench. The method makes it possible to solve problems caused by impurities present in material with which the trench is gap-filled or present in etchants used in an etch-back process.Type: ApplicationFiled: December 21, 2007Publication date: September 4, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Chan Sun Hyun
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Publication number: 20080200678Abstract: The present invention relates to a light-emitting transition metal compound represented by the Chemical Formula 1 and Chemical Formula 2 and an organic electroluminescence device including the same. In the Chemical Formulae 1 and 2, M is Ir, Pt, Rh, Re, Os, and the like, m is 2 or 3, n is 0 or 1, the sum of m and n is 3, provided that the sum of m and n is 2 when M is Pt, X, and Z are the same or different, N or P, and Y and Q are O, S, or Se, R1 and R5 are hydrogen, a C1 to C20 alkyl excluding an aromatic cyclic substituent, a cycloalkyl, a halogen, a linear or branched substituent including at least one halogen, or a linear or branched substituent including at least one heteroatom, and R2, R3, R4, R6, R7, R8, R9, and R10 are hydrogen, a C1 to C20 alkyl, an aryl, a cycloalkyl, a halogen, a linear or branched substituent including at least one halogen, a linear or branched substituent including at least one heteroatom, carbonyl, vinyl, or acetylenyl, or may form a cycle, and may be the same or different.Type: ApplicationFiled: January 8, 2007Publication date: August 21, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.,Inventors: Dong-Hack Suh, Jin-Soo Lim, Ji-Ho Kim, Sun-Hyun Choi
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Patent number: 7413858Abstract: Disclosed is a method for identifying Streptomyces species using groEL2 gene that can compensate for drawbacks of conventional methods of morphologic classification and 16S rDNA identification being time-consuming, unfaithful, and expensive, thus enabling to efficiently identify Streptomyces species.Type: GrantFiled: April 15, 2004Date of Patent: August 19, 2008Assignee: Korea Research Institute of Bioscience and BiotechnologyInventors: Bum-Joon Kim, Chang-Jin Kim, Young Hwan Ko, Jeong-Sam Koh, Dong-Jin Park, Hyang Burm Lee, Hong Kim, Sun-hyun Kim
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Publication number: 20080160760Abstract: A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a second etching stop layer on the first etching stop layer; forming an insulating layer on the second etching stop layer; removing the insulating layer placed between the select lines, the second etching stop layer and the first etching stop layer to form a contact hole through which a portion of the semiconductor substrate is exposed; and filling the contact hole with conductive material to form a contact plug, and so the nitride layer is thinly formed and the high dielectric layer is then formed to form the etching stop layer. Due to the above, a layer stress caused by the nitride layer can be minimized, and it is possible to resolve a problem of exposing the semiconductor substrate caused by a damage of the etching stop layer.Type: ApplicationFiled: May 11, 2007Publication date: July 3, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Chan Sun Hyun