Patents by Inventor An-Tai Huang

An-Tai Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170221576
    Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Inventors: Chen-Yi HUANG, Jiaqi YANG, Cheng-Tai HUANG
  • Publication number: 20170221575
    Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.
    Type: Application
    Filed: April 20, 2017
    Publication date: August 3, 2017
    Inventors: Chen-Yi HUANG, Jiaqi YANG, Cheng-Tai HUANG
  • Patent number: 9696391
    Abstract: A precision high-speed shuttle device for transporting samples between different positions of a superconducting magnet with different magnetic field strength is provided. The sample equilibrated at the center of the magnet, where the magnetic field is the highest and homogeneous, is shuttled to a higher position above, where the fringe field is lower, for a defined period of time and shuttled back to the center for detection. By shuttling the sample to different positions in the magnet in different experiments one can obtain a field-dependent profile of particular physical parameters. The position and timing of the sample are precisely under the experimental controlled. In this way various magnetic field-dependent nuclear magnetic resonance (NMR) experiments can be conducted in a single high-field NMR spectrometer.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: July 4, 2017
    Assignee: ACADEMIA SINICA
    Inventors: Tai-Huang Huang, Ching-Yu Chou, Ming-Lee Chu, Chi-Fon Chang
  • Publication number: 20170177141
    Abstract: A pressure detection method for an in-cell touch display and a mobile device using the same are provided. The pressure detection method comprises the steps of: providing a common voltage plane corresponding to touch sensing electrodes in the in-cell touch display; detecting capacitance values of the touch sensing electrodes; setting a first area and a second area according to a center of a touched portion when the in-cell touch display is determined as being touched, wherein the second area includes the first area; and excluding the capacitance values of the touch sensing electrodes in the first area, and using the capacitance values of the touch sensing electrodes in the second area to serve as a pressure detection value to determine a pressure exerted on the in-cell touch display.
    Type: Application
    Filed: September 27, 2016
    Publication date: June 22, 2017
    Inventors: Po-Sheng SHIH, CHIEN-YUNG CHENG, Cheng-Tai HUANG
  • Patent number: 9659672
    Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 23, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Chen-Yi Huang, Jiaqi Yang, Cheng-Tai Huang
  • Patent number: 9620239
    Abstract: A method for operating a memory is provided. The memory has an array of memory cells arranged in a plurality of rows and columns. Each row includes a label storage unit. The method includes receiving a first to-be-programmed data set to be stored into a target row and determining whether a condition is satisfied. When the condition is satisfied, performing a first operation on the first to-be-programmed data set to obtain a second to-be-programmed data set, programming the second to-be-programmed data set into the target row of memory cells, and setting the value of the label storage, unit to be a first labeling value. When the condition is not satisfied, performing a second operation on the first to-be-programmed data set to program the first to-be-programmed data set into the target row of memory cells, and setting the value of the label storage unit to be a second labeling value.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 11, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Cheng-Tai Huang, Chia-Chi Yang, Chen-Yi Huang
  • Patent number: 9601388
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Jr-Jung Lin, Chien-Hao Chen, Yi-Hsing Chen, Kuo-Tai Huang, Yih-Ann Lin, Yi-Shien Mor
  • Patent number: 9569051
    Abstract: A method for determining touch point coordinates on capacitive type touch panel includes following steps. A touch panel having a conductive layer, a plurality of first electrodes, and a plurality of second electrodes is provided. A first signal curve As1 is obtained by driving and sensing each first electrode. A second signal curve As2 is obtained by driving and sensing each second electrode. A third signal curve Bs1 is obtained by driving and sensing each first electrode, wherein the second electrode opposite to the sensed first electrode is grounded. A fourth signal curve Bs2 is gotten by driving and sensing each second electrodes, wherein the first electrode opposite to the sensed second electrode is grounded. The coordinates of the touch points are obtained by comparing the first signal curve As1, the second signal curve As2, the third signal curve Bs1, and the fourth signal curve Bs2.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: February 14, 2017
    Assignee: TIANJIN FUNAYUANCHUANG TECHNOLOGY CO., LTD.
    Inventors: Chien-Yung Cheng, Cheng-Tai Huang, Chun-Lung Huang, Feng-Yu Kuo, Po-Sheng Shih
  • Patent number: 9564488
    Abstract: A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mong-Song Liang, Tze-Liang Lee, Kuo-Tai Huang, Chao-Cheng Chen, Hao-Ming Lien, Chih-Tang Peng
  • Publication number: 20160293490
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
    Type: Application
    Filed: January 29, 2016
    Publication date: October 6, 2016
    Inventors: Ryan Chia-Jen Chen, Jr-Jung Lin, Chien-Hao Chen, Yi-Hsing Chen, Kuo-Tai Huang, Yih-Ann Lin, Yi-Shien Mor
  • Patent number: 9418763
    Abstract: The present invention provides a memory. The memory includes a plurality of memory cells arranged as an array with a plurality of rows and a plurality of column. A memory cell is connected to at least one redundant memory cell in a same row for storing same data as the memory cell; and a column of memory cells correspond to one redundant column of redundant memory cells wherein each redundant memory cell in the redundant column stores same data as the memory cell in a same row.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: August 16, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Cheng-Tai Huang, Jiaqi Yang, Chen-Yi Huang
  • Publication number: 20160133525
    Abstract: In a method of manufacturing a semiconductor device, a first gate structure and a second gate structure are formed on a substrate in a first region and a second region, respectively. A first semiconductor pattern including germanium is formed in the first region on the substrate. A first metal layer is formed on the substrate to cover the first semiconductor pattern. A first heat treatment process is performed such that the first semiconductor pattern and the first metal layer react with each other to form a first metal-semiconductor composite pattern in the first region and a semiconductor material of the substrate and the first metal layer react with each other to form a second metal-semiconductor composite pattern in the second region. The first metal-semiconductor composite pattern is removed from the substrate. A second metal layer is formed on the substrate to cover the second metal-semiconductor composite pattern. The second metal layer includes a material different from the first metal layer.
    Type: Application
    Filed: October 2, 2015
    Publication date: May 12, 2016
    Inventors: Joon-Gon LEE, Ryuji TOMITA, Sang-Jin HYUN, Kuo Tai HUANG
  • Publication number: 20160108121
    Abstract: Combinations of anti-cancer antibodies and inhibitory antibodies to CD223 overcome immune suppression in cancer patients. The inhibitory antibodies may be generated in an animal by injection of fragments of CD223. Antibodies may be monoclonal antibodies or single chain antibodies or humanized antibodies.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 21, 2016
    Applicants: The Johns Hopkins University, St. Jude's Children's Research Hospital Inc.
    Inventors: Drew M. Pardoll, Ching-Tai Huang, Jonathan Powell, Charles Drake, Dario A. Vignali, Creg J. Workman
  • Publication number: 20160098738
    Abstract: The present invention is related to an issue-manage-style internet public opinion information evaluation management system and method thereof. The system mainly comprises 5 modules of 1) Issue establish/setup module for establishing new issue and the keywords thereof; 2) public opinion information collection module for retrieving and analyzing data retrieved by dredge technology, program, and community web-site open API; 3) public opinion information reputation analysis module for calculating each public opinion information evaluation score by text reputation analysis and community interactive fuzzy analysis; 4) issue trend analysis module for calculating issue trend score by disclosed method based on daily, weekly, or monthly public opinion information reputation evaluation score; 5) issue related public opinion information exchange module for presenting issue related public opinion information on each management interface or message alert of each system via internet exchange standards.
    Type: Application
    Filed: February 4, 2015
    Publication date: April 7, 2016
    Inventors: HUA-TAI HUANG, MENG-HSIN YANG, PO-WEI HUANG
  • Patent number: 9263445
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
  • Patent number: 9257426
    Abstract: A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yi-Shien Mor, Yi-Hsing Chen, Kuo-Tai Huang, Chien-Hao Chen, Yih-Ann Lin, Jr Jung Lin
  • Publication number: 20160035439
    Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.
    Type: Application
    Filed: July 27, 2015
    Publication date: February 4, 2016
    Inventors: CHEN-YI HUANG, JIAQI YANG, CHENG-TAI HUANG
  • Publication number: 20160035434
    Abstract: The present invention provides a memory. The memory includes a plurality of memory cells arranged as an array with a plurality of rows and a plurality of column. A memory cell is connected to at least one redundant memory cell in a same row for storing same data as the memory cell; and a column of memory cells correspond to one redundant column of redundant memory cells wherein each redundant memory cell in the redundant column stores same data as the memory cell in a same row.
    Type: Application
    Filed: July 27, 2015
    Publication date: February 4, 2016
    Inventors: CHENG-TAI HUANG, JIAQI YANG, CHEN-YI HUANG
  • Patent number: 9226434
    Abstract: An electrically-conducting assembly for conducting a first housing and a second housing of an electronic device. The first housing is detachably combined with the second housing. The electrically-conducting assembly includes a retaining wall and a lapping part. The retaining wall is perpendicularly provided at the first housing, and a surface of the retaining wall has an electrically-conducting layer. The lapping part is perpendicularly provided at the second housing, and a surface of the lapping part has another electrically-conducting layer. The lapping part and the retaining wall contact with each other when the first housing and the second housing are combined so that the electrically-conducting layer and the another electrically-conducting layer are mutually conductive.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: December 29, 2015
    Assignee: PEGATRON CORPORATION
    Inventors: Su-Tai Huang, Dun-Wei Su
  • Publication number: 20150361580
    Abstract: The present invention provides a device and method of use the device for simultaneously producing multiple silicon carbide crystals. The device comprises: a reaction unit comprising a cylindrical crucible and a circular cover corresponding to the cylindrical crucible; a thermal insulation material arranged above, below, and peripherally around the reaction unit; a reaction enclosure surrounding the reaction unit and the thermal insulation material; and a heating system corresponding to and encircling the reaction enclosure; wherein the cylindrical crucible has a side provided with a rotating mechanism for driving the cylindrical crucible into rotation, and the thermal insulation material above the reaction unit is arranged on the circular cover and has a thickness decreasing from a center of the circular cover toward a rim of the circular cover.
    Type: Application
    Filed: December 29, 2014
    Publication date: December 17, 2015
    Inventors: Chun-Hui HUANG, Tai-Huang LIN, Ching-Kun MAI