Abstract: An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.

Abstract: Described herein is a graphics processor comprising an instruction cache and a plurality of processing elements coupled with the instruction cache. The plurality of processing elements include functional units configured to provide an integer pipeline to execute instructions to perform operations on integer data elements. The integer pipeline including a first multiplier and a second multiplier, the first multiplier and the second multiplier configured to execute operations for a single instruction.

Abstract: Provided are single-domain antibodies targeting CLL1 and constructs thereof, including chimeric receptors, immune effector cell engagers and immunoconjugates. Further provided are engineered immune effector cells (such as T cells) comprising an anti-CLL1 chimeric receptor and optionally a second chimeric receptor targeting a second antigen or epitope. Pharmaceutical compositions, kits and methods of treating cancer are also provided.

Abstract: The present application provides GPC2-specific antibodies and antigen binding fragments thereof. A chimeric antigen receptor (CAR) that specifically binds glypican-2 (GPC2) comprising a GPC2-specific antibody, a transmembrane domain, and an intracellular signaling domain. T cells comprising the disclosed CAR constructs can be used for cancer immunotherapy.

Abstract: An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.

Abstract: An electronic glasses includes a lens frame, a first temple, a second temple, an electronic device and an audio I/O device. The Hall sensor is disposed at one of the lens frame, the first template, and the second temple. The audio I/O device is disposed at another of the lens frame, the first temple and the second temple, and provided with a magnetic element. The Hall sensor provides a first signal for the electronic device when the first temple and/or the second temple are folded to make the Hall sensor and the audio I/O device close to each other, and the Hall sensor provides a second signal for the electronic device when the first temple or the second temple are unfolded to make the Hall sensor and the audio I/O device be away from each other.

Abstract: Provided herein are anti-DLL3 chimeric antigen receptors (CARs), DLL3 binding proteins and uses of such CARs or DLL3 binding proteins in the treatment of DLL3 associated disorders, such as small cell lung cancer.

Abstract: Provided are single-domain antibodies targeting CLL1 and constructs thereof, including chimeric receptors, immune effector cell engagers and immunoconjugates. Further provided are engineered immune effector cells (such as T cells) comprising an anti-CLL1 chimeric receptor and optionally a second chimeric receptor targeting a second antigen or epitope. Pharmaceutical compositions, kits and methods of treating cancer are also provided.

Abstract: A fingerprint sensing system has a fingerprint sensing device and a power supply circuit. The fingerprint sensing device has a high-voltage input terminal and a low-voltage input terminal. During scan phases of the fingerprint sensing device, the power supply circuit provides a first voltage to the high voltage input terminal and provides a second voltage to the low voltage input terminal. During the read phases of the fingerprint sensing device, the power supply circuit provides a third voltage to the high voltage input terminal and provides a fourth voltage to the low voltage input terminal. A first voltage difference is between the first voltage and the second voltage. A second voltage difference is between the third voltage and the fourth voltage. The first voltage difference is greater than the second voltage difference.

Abstract: A fingerprint sensor having electrostatic discharge (ESD) protection includes a first ESD protection electrode and a second ESD protection electrode. The first ESD protection electrode is connected to an ESD protection circuit for providing an ESD path, where the first ESD protection electrode and a fingerprint sensor electrode array are formed in a same layer of the fingerprint sensor. The second ESD electrode is connected to the first ESD electrode via multiple conductive via.

Abstract: Described herein are technologies related to enforcing thread dependency using a hybrid scoreboard. An encoded video information that includes a plurality of threads is received, a first set and a second set of threads from the plurality of thread is determined, the first and second sets of threads are assigned to a hardware and a software, respectively, and dependency threads in the first and second sets of threads is enforced.

Abstract: A fingerprint sensing system has a fingerprint sensing device and a power supply circuit. The fingerprint sensing device has a high-voltage input terminal and a low-voltage input terminal. During scan phases of the fingerprint sensing device, the power supply circuit provides a first voltage to the high voltage input terminal and provides a second voltage to the low voltage input terminal. During the read phases of the fingerprint sensing device, the power supply circuit provides a third voltage to the high voltage input terminal and provides a fourth voltage to the low voltage input terminal. A first voltage difference is between the first voltage and the second voltage. A second voltage difference is between the third voltage and the fourth voltage. The first voltage difference is greater than the second voltage difference.

Abstract: In an embodiment, at least one computer readable storage medium has instructions stored thereon for causing a system to send, from a processor to a task execution device, a first call to execute a first subroutine of a set of chained subroutines. The first subroutine may have a first subroutine output argument that includes a first token to indicate that first output data from execution of the first subroutine is intermediate data of the set of chained subroutines. The instructions are also for causing the system, responsive to inclusion of the first token in the first subroutine output argument, to enable the processor to execute one or more operations while the task execution device executes the first subroutine. Other embodiments are described and claimed.

Abstract: A fingerprint sensor having electrostatic discharge (ESD) protection includes a first ESD protection electrode and a second ESD protection electrode. The first ESD protection electrode is connected to an ESD protection circuit for providing an ESD path, where the first ESD protection electrode and a fingerprint sensor electrode array are formed in a same layer of the fingerprint sensor. The second ESD electrode is connected to the first ESD electrode via multiple conductive via.

Abstract: Systems and methods may receive an input image for data processing, divide the input image into a plurality of blocks, each block including a plurality of rows, and each row including a plurality of pixels and process each pixel in the input image within a row in parallel with a user-defined template. In one example, the user-defined template is to include a structuring element and a row pixel mask.

Abstract: In an embodiment, at least one computer readable storage medium has instructions stored thereon for causing a system to send, from a processor to a task execution device, a first call to execute a first subroutine of a set of chained subroutines. The first subroutine may have a first subroutine output argument that includes a first token to indicate that first output data from execution of the first subroutine is intermediate data of the set of chained subroutines. The instructions are also for causing the system, responsive to inclusion of the first token in the first subroutine output argument, to enable the processor to execute one or more operations while the task execution device executes the first subroutine. Other embodiments are described and claimed.

Abstract: A fingerprint sensor having ESD protection structure and has a substrate having an upper surface. Multiple sensing electrode plates, an ESD protection electrode part connected to ground, a dielectric layer and a protection layer are formed on the upper surface in bottom-up sequence. The ESD protection layer has a first conductive layer and a second conductive layer. The first conductive layer is formed on the upper surface and coplanar with the sensing electrode plates. The second conductive layer is formed on the dielectric layer and has multiple separated conductive elements. Each of conductive elements overlaps the first conductive layer along a vertical axis and connected to the first conductive layer via multiple vias formed in the dielectric layer. When the first conductive layer and/or the second conductive layer are/is coupled to ground, both of the first and second conductive layers are established a discharging path of static electricity.

Abstract: Described herein are technologies related to a method of enforcing thread dependencies using a hybrid scoreboard-based approach.

Abstract: Systems and methods may determine a boundary value data unit in a large data set in parallel with determining an associated index of the determined boundary value data unit into the large data set using a single instruction multiple data (SIMD) instruction set architecture and a specialized data layout of array entries. In one example, the specialized data layout of array entries combines a data value and its associated index to an array into a single array entry.

Abstract: A method for generating a layout for a cell of an integrated circuit (IC) guided by design rule checking (DRC) is disclosed. In the method, a model is defined, wherein the model comprises a plurality of parameters for generating a layout of the cell. Next an initial layout for the cell can be generated according to an initial set of values for the plurality of parameters. Then design rule checking (DRC) is performed for the initial layout based on a set of design rules. If any violations are found, the corresponding violation reports will be associated with the model. Therefore, a new set of values for the plurality of parameters can be generated by analyzing the violation reports collectively based on the model. With the new set of values for the plurality of parameters and above steps repeated, until no violation is found, a “DRC clean” layout can be generated.