Patents by Inventor An Trinh

An Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250094988
    Abstract: Systems, methods and computer-readable storage media utilized to complete a cardless transaction on a distributed ledger network. One method includes receiving, by a point-of-sale (POS) computing device, a transaction request including a biometric sample from an individual associated with a payment account at a financial institution. The method further includes authenticating, by the POS computing device, the biometric sample by cross-referencing the biometric sample with a biometric dataset stored on the distributed ledger network. The method further includes, in response to authenticating the biometric sample, generating, by the POS computing device, a cryptogram associated with the biometric sample and processing, by the POS computing device, the transaction request utilizing the cryptogram.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 20, 2025
    Applicant: Wells Fargo Bank, N.A.
    Inventors: DUC M. TRINH, NIKOLAI STROKE, HARMIT SINGH DHANOA
  • Patent number: 12254476
    Abstract: This disclosure provides systems and methods for matching a customer with a service representative. A request for service can be received from a customer. A first service interaction can be initiated between the customer and a first service representative. A customer sentiment metric can be determined during the first service interaction. The customer sentiment metric can indicate a level of customer satisfaction during the first service interaction. A second service representative suitable for fulfilling the customer's request for service can be identified, based at least in part on the customer sentiment metric. A second service interaction can be initiated between the customer and the second service representative, responsive to the identification of the second service representative.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: March 18, 2025
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Wayne Barakat, Thomas E. Gross, Darius Miranda, Marria Wairmola Rhodriquez, Andres J. Saenz, Sadie Salim, Duc M. Trinh
  • Publication number: 20250083828
    Abstract: An exhaust nozzle for an aircraft propulsion system includes a nozzle wall and a nozzle ring. The nozzle wall extends axially along an axis from an upstream end of the nozzle wall to a downstream end of the nozzle wall. The nozzle wall includes an inner skin, an outer skin and a cellular core between the inner skin and the outer skin. The inner skin forms an outer peripheral boundary of a flowpath axially along the nozzle wall. The nozzle ring forms a downstream trailing edge of the exhaust nozzle. The nozzle ring projects axially out from the downstream end of the nozzle wall to the downstream trailing edge of the exhaust nozzle to form another outer peripheral boundary of the flowpath axially along the nozzle ring. The nozzle ring is axially abutted against the cellular core. The nozzle ring is bonded to the inner skin and the outer skin.
    Type: Application
    Filed: September 11, 2024
    Publication date: March 13, 2025
    Inventors: William Mclennan, Joseph R. Lundin, Nhi H. Trinh, Mark A. Ramsey, Kevin P. Aceves, Matthew J. DelConte, Khandaker T. Walid, Brittney Depiano, Johann Schrell, Jason Habchi
  • Patent number: 12249766
    Abstract: The invention relates to a dual polarized wideband array antenna using orthogonal feeding technique to have a low profile and a cosecant squared beam. The array antenna includes three main parts: the element antennas, the orthogonal feeding structure and the feeding network. The spatially orthogonal feeding structure is a transition between the microstrip lines on element antennas and the striplines on the feeding network. The top layer of the feeding network operates as a ground plane for the array antenna. Due to the disparities between the stripline lengths, the phase parameters of element antennas are optimized to create a cosecant squared radiation pattern.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: March 11, 2025
    Assignee: VIETTEL GROUP
    Inventors: Tien Manh Nguyen, Ngoc Anh Trinh, Cong Kien Dinh, Manh Linh Nguyen
  • Publication number: 20250079199
    Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: Shiyu YUE, Sahil Jaykumar PATEL, Yu LEI, Wei LEI, Chih-Hsun HSU, Yi XU, Abulaiti HAIRISHA, Cong TRINH, Yixiong YANG, Ju Hyun OH, Aixi ZHANG, Xingyao GAO, Rongjun WANG
  • Publication number: 20250081864
    Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: HAI-DANG TRINH, FA-SHEN JIANG, HSING-LIEN LIN, CHII-MING WU
  • Patent number: 12245529
    Abstract: Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Albert Zhong, Cheng-Yuan Tsai, Hai-Dang Trinh, Shing-Chyang Pan
  • Patent number: 12243587
    Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: March 4, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Stephen Trinh, Stanley Hong, Thuan Vu, Anh Ly, Fan Luo
  • Publication number: 20250071549
    Abstract: Disclosed are example methods, systems, and devices that allow for the generation and provisioning of digital credentials, which may demonstrate that a trusted entity has validated individual identity attributes, or sets of attributes, of a user. Digital credentials may also demonstrate one or more extrapolations resulting from deductions or inductions from validated identity attributes. A receiver device may indicate which identity attributes or extrapolations are sought by displaying a QR or other code and/or via a transmission using NFC or other wireless communication, and a user device may access corresponding digital attributes in an ID wallet to be provisioned via code or transmission. Digital credentials may restrict uses and usability of identity attributes. Cryptographic keys and/or distributed ledger records may allow recipients to verify authenticity of digital credentials. The same identity attribute may be proven by showing validation by multiple selectable trusted entities.
    Type: Application
    Filed: November 11, 2024
    Publication date: February 27, 2025
    Applicant: Wells Fargo Bank, N.A.
    Inventors: Harmit Singh Dhanoa, Andrew G. Foote, Nikolai Stroke, Duc M. Trinh
  • Publication number: 20250068861
    Abstract: Numerous examples are disclosed of input blocks for an array of non-volatile memory cells and associated methods. In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an input block comprising a plurality of row circuits and a global digital-to-analog converter generator to generate 2m different analog voltages, where m is an integer; wherein the row circuits in the plurality of row circuits respectively apply one of the 2m different analog voltages to an associated row in the array.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 27, 2025
    Inventors: Hieu Van Tran, Stephen Trinh, Hoa Vu, Stanley Hong, Thuan Vu
  • Patent number: 12234465
    Abstract: Genetically modified microorganisms that have the ability to convert carbon substrates into chemical products such as isobutanol are disclosed. For example, genetically modified methanotrophs that are capable of generating isobutanol at high titers from a methane source are disclosed. Methods of making these genetically modified microorganisms and methods of using them are also disclosed.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: February 25, 2025
    Assignee: PRECIGEN, INC.
    Inventors: Jeffrey David Orth, Louis A. Clark, Lily Yuin Chao, Na My Trinh, Christopher Cheyney Farwell, Xinhua Zhao, Matthias Helmut Schmalisch, Grayson Thomas Wawrzyn, Xuezhi Li, Mark Anton Held, Kevin Lee Dietzel, James Kealey
  • Patent number: 12239035
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory device. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first atomic percentage of a first dopant and a second atomic percentage of a second dopant. The first atomic percentage is different from the second atomic percentage. A top electrode is formed on the data storage structure.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Tzu-Chung Tsai, Fa-Shen Jiang, Bi-Shen Lee
  • Patent number: 12239015
    Abstract: Disclosed herein are organic photosensitive optoelectronic devices comprising acceptor and/or donor sensitizers to increase absorption and photoresponse of the photoactive layers of the devices. In particular, devices herein include at least one acceptor layer and at least one donor layer, wherein the acceptor layer may comprise a mixture of an acceptor material and at least one sensitizer, and the donor layer may comprise a mixture of a donor material and at least one sensitizer. Methods of fabricating the organic photosensitive optoelectronic devices are also disclosed.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: February 25, 2025
    Assignee: University of Southern California
    Inventors: Mark E. Thompson, Cong Trinh, Peter I. Djurovich, Sarah M. Conron
  • Patent number: 12237011
    Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: February 25, 2025
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Stephen Trinh, Anh Ly, Han Tran, Kha Nguyen, Hien Pham
  • Patent number: 12232336
    Abstract: A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.
    Type: Grant
    Filed: November 10, 2023
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Fa-Shen Jiang, Hsia-Wei Chen, Hai-Dang Trinh, Hsun-Chung Kuang
  • Patent number: 12232434
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage structure is formed on the bottom electrode. The data storage structure comprises a first dopant with a first atomic percent and a second dopant with a second atomic percent. The first atomic percent is different from the second atomic percent. A top electrode is formed on the data storage structure.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bi-Shen Lee, Hai-Dang Trinh, Fa-Shen Jiang, Hsun-Chung Kuang
  • Patent number: 12226957
    Abstract: Systems and method for producing a small-scale mixer are provided. In some implementations, a method for includes obtaining dimensions of an at-scale mixer. The method also includes determining first dimensions of the small-scale mixer based on respective dimensions of the at-scale mixer. The method further includes determining second dimensions of the small-scale mixer independent of the dimensions of the at-scale mixer. Additionally, the method includes generating the small-scale mixer using the first dimensions and the second dimensions using a three-dimensional printer.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: February 18, 2025
    Assignee: Regeneron Pharmaceuticals, Inc.
    Inventors: Trinh Vo, Huyun Chen, Amardeep Singh Bhupender Bhalla
  • Publication number: 20250052438
    Abstract: Provided are an air purifying system and method adapted for a movable enclosed space. The air purifying system includes a charged gas generating source, a blowing system, a circulation system, and one or more electrical neutralization devices. The electrical neutralization devices are disposed in the movable enclosed space to neutralize charged gas in the movable enclosed space. The charged gas generating source which generates the charged gas with negative ions in high concentration and the electrical neutralization devices disposed in the movable enclosed space not only enable persons in the movable enclosed space to access high-quality air but also preclude any adverse impact of negative ions in high concentration on important electrical equipment.
    Type: Application
    Filed: August 2, 2024
    Publication date: February 13, 2025
    Inventors: Vicki-Fen CHOU, Philip TRINH, Christine TRINH
  • Publication number: 20250050144
    Abstract: Provided is a fireproof partition including: two fireproof boards made of a fireproof material; a support board disposed between the two fireproof boards; a fixing means for fixing the two fireproof boards to two opposing sides of the support board respectively, allowing the support board to be sandwiched between the two fireproof boards; and a hanging means provided on an outer side of one of the two fireproof boards and adapted to operate in conjunction with a building.
    Type: Application
    Filed: July 23, 2024
    Publication date: February 13, 2025
    Inventors: Vicki-Fen Chou, Philip Trinh, Christine Trinh
  • Patent number: D1062934
    Type: Grant
    Filed: March 8, 2024
    Date of Patent: February 18, 2025
    Inventor: Trinh Nguyen Khanh Le