Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: The present application relates to a temperature adjustment device, a single-phase liquid cooling system and a control method for a single-phase liquid cooling system. The temperature adjustment device includes a first casing, a second casing, a first valve body, a second valve body, and a phase transition material. The first casing is provided with a first chamber therein, and the first casing is provided with a liquid inlet, a first liquid outlet, and a second liquid outlet which are in communication with the first chamber. The second casing is provided with a second chamber therein, and the second casing is arranged within the first chamber. The first valve body has a first plugging position for isolating the first liquid outlet from the liquid inlet, and a first opening position for allowing communication between the first liquid inlet and the first liquid outlet.

Abstract: Embodiments of the present application provide a power supply system and method of a server, an electronic device, and a storage medium. By means of cooperative work of main circuit structures such as a high-voltage battery power master control unit, battery string management and control units, and power conversion string management and control units, power information of each subsystem in the power supply system is collected and analyzed in real time, and the high-voltage battery power master control unit can also issue a corresponding control instruction to each subsystem according to the analysis result so as to realize power control of each subsystem, thereby controlling the total output power of the server.

Abstract: A method includes: coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction; coupling the first gate to a second word line through a second gate via, wherein each of the first gate, a second gate, the first gate via and the second gate via is disposed on a first active area which extends along the second direction, wherein the second gate extends along the first direction and is separated from the first gate along a second direction; coupling the first active area to a first bit line through a first conductive via; and aligning the first gate via, the second gate via and the a first conductive via with each other along the second direction.

Abstract: A foam is provided. The foam includes a foaming material and a plurality of cells arranged within the foaming material. The foaming material is prepared from a composition, which includes 0.01-2.0 parts by weight of a flow aid and 100 parts by weight of a block copolymer. The block copolymer includes a first block, a second block, and a linking moiety. The first block is connected to the second block via the linking moiety. The first block is an aromatic polyester block. The second block is an aliphatic polyether block, an aliphatic polyester block, or an aliphatic polycarbonate block. The linking moiety is a residue of a dehydrogenated polyol.

Abstract: An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: The present invention provides a control method of a flash memory controller. By dividing a plurality of logical address to physical address mapping tables into multiple groups, establishing a group-to-physical address mapping table, a storage unit relationship table and a latest updated storage unit table to manage the flash memory controller, the times of loading the group-to-physical address mapping table into a buffer memory can be reduced, so as to improve the efficiency of the flash memory controller.

Abstract: An electronic device including a first body, a second body, a pivoting shaft, a driving module, and a light source is provided. The first body includes a first casing and a second casing movably disposed on the first casing. The second body has a pivoting part and a light reflecting part located at the pivoting part. The pivoting shaft is connected to the pivoting part. The second body is pivoted to the first body through the pivoting shaft. The pivoting shaft, the driving module, and the light source are disposed in the first body. The driving module is connected to the pivoting shaft and contacts the second casing. When the second body rotates relative to the first body, the pivoting shaft drives the driving module to push the second casing to lift to form a light emitting slit between the second casing and the pivoting part.

Abstract: A circuit board structure is provided. The circuit board structure includes a first insulating layer, a second insulating layer, a vertical conductive feature, and an electronic element. The first insulating layer has multiple bumps thereon. The second insulating layer is disposed on the first insulating layer. The vertical conductive feature includes a first via hole and a second via hole extending vertically in the first insulating layer. The electronic element is disposed in the second insulating layer and surrounded by the bumps. The electronic element is electrically connected to the first via hole.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: The instant disclosure provides a gate device and an umbrella sharing system which utilizes the gate device. The gate device includes a base, an actuator, a pair of gate plates, and an identification sensor. The actuator is disposed on a top surface of the base and includes a latch extending downward through the base. The pair of gate plates are disposed on a bottom surface of the base, and each of the gate plates includes a guiding structure and a locking structure. A waiting zone for receiving an umbrella is defined between the two guiding structures. The latch of the actuator is driven to engage with the locking structures to limit the movement of the gate plates. The identification sensor is above the waiting zone and disposed on the base and is configured to identify the identity of an umbrella which enters the waiting zone.

Abstract: A cell culture device configured for activating, transducing, isolating and/or expanding cells. The cell culture device includes a mixing tank and a rotary control platform. The mixing tank includes a first support, a hollow tank and a cover. The hollow tank is disposed on the first support and has a first opening, a second opening and an accommodating space. The cover covers the second opening and has a first hole, an inlet end and an outlet end. The rotary control platform includes a base, a second support, a rotating gear, an inclination control member and a micro injector. The second support is disposed on the base. The rotating gear is fixed on the first support. The inclination control member has a first part, a second part and a third part. The first part is connected to the rotating gear, and the second part is connected to the first part and the third part. The micro injector extends to the accommodating space through the first hole of the cover.

Abstract: A magnetic separation device includes a sleeve and two fixing portions. The sleeve includes a sleeve body and a hollow portion. The hollow portion penetrates through the sleeve body. The two fixing portions are individually disposed oppositely to a first end and a second end of the sleeve body. Each of the two fixing portions includes a protruding body and a groove. The protruding body is protruded out from an outer surface of the sleeve body, and the groove is disposed at an outer surface of the protruding body.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A sports shoe is provided. The sports shoe includes a shoe vamp and a shoe sole connected to the shoe vamp. The shoe vamp includes a textile component, wherein the textile component includes thermoplastic polyester fibers. The shoe sole includes a shoe outsole and a shoe midsole foam disposed between the shoe outsole and the shoe vamp, wherein the shoe outsole includes a vulcanizate and the shoe midsole foam includes a first thermoplastic elastomer. The vulcanizate includes rubber particles, a second thermoplastic elastomer, and an interface-compatible resin, wherein the content of the rubber particles is greater than the content of the second thermoplastic elastomer. The rubber particles are dispersed in the second thermoplastic elastomer in the form of spherical particles with particle sizes of about 0.5-10 um.

Abstract: A thermoplastic vulcanizate is provided. The thermoplastic vulcanizate includes: (A) about 100 parts by weight of a styrene copolymer rubber; (B) about 40-90 parts by weight of a thermoplastic elastomer; (C) about 5-15 parts by weight of an interfacial compatible resin; and (D) about 0.2-3 parts by weight of a cross-linking formulation, wherein the content of component (A) is greater than the content of component (B). Component (A) is dispersed in component (B) in the form of particles with a particle size of about 0.5-10 ?m.