Abstract: The present invention relates to a pharmaceutical composition for use preventing and curing respiratory diseases in winter. The composition comprises burdock seeds, blackberry lily, Platycodon grandiflorus, radix paeoniae rubra, Perilla frutescens, honeysuckle, fructus crataegi, Astragalus membranaceus, Reynoutria japonica, Glycyrrhiza uralensis, and non-essential fermented tea. The present invention also relates to a pharmaceutical preparation use of the pharmaceutical composition. The pharmaceutical composition can be used for nourishing Qi, moistening lungs, clearing throats, relieving sore throats and/or decontaminating, and can be used for preparing a pharmaceutical for treating and/or preventing pharyngitis.

Abstract: The present invention relates to a wire bonding structure with an embedded manifold type micro-channel. The wire bonding structure includes: a chip, including a substrate and an embedded micro-channel located on a back portion of the substrate; an interposer, including a manifold channel, a liquid inlet, and a liquid outlet; a low-temperature sealing layer, configured to hermetically communicate the embedded micro-channel with the manifold channel, wherein the low-temperature sealing layer is located between the chip and the interposer; and a bonding wire, configured to electrically connect the chip to the interposer. The present invention further relates to a preparation method of a wire bonding structure with an embedded manifold type micro-channel. The wire bonding structure of the present invention has both low-temperature process compatibility and packaging compatibility, and further has high heat dissipation efficiency.

Abstract: Exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The metal-doped boron-containing material may include a metal dopant comprising tungsten. The substrate may include a silicon-containing material. The methods may include depositing one or more additional materials over the metal-doped boron-containing material. The one or more additional materials may include a patterned photoresist material. The methods may include transferring a pattern from the patterned photoresist material to the metal-doped boron-containing material. The methods may include etching the metal-doped boron-containing material with a chlorine-containing precursor. The methods may include etching the silicon-containing material with a fluorine-containing precursor. The metal dopant may enhance an etch rate of the silicon-containing material.

Abstract: A battery pack and an electric apparatus are disclosed. The battery pack includes a cell dummy and multiple battery cells, a housing, a mounting beam, and a support beam. The housing is provided with an accommodating cavity, and the cell dummy and the multiple battery cells are all disposed in the accommodating cavity. The mounting beam is disposed in a length direction of the accommodating cavity and defines, together with the accommodating cavity, a mounting space for accommodating the cell dummy and the multiple battery cells. The support beam is disposed in a width direction of the accommodating cavity and is mounted in a manner of fitting with the cell dummy. The cell dummy being provided with the support beam perpendicular to the mounting beam can enhance structural strength of the battery pack in the width direction of the accommodating cavity.

Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, a stressor layer is formed in the source/drain space, a metal gate structure including part of the second semiconductor layer as channel regions is formed by a gate replacement process, after the metal gate structure is formed, the stressor layer is at least partially removed, and a source/drain contact comprising metal or a metallic material is formed in the source/drain space from which the stressor layer is at least partially removed.

Abstract: An atomization core includes: a seat comprising an atomization chamber; a liquid guiding member arranged inside the atomization chamber for guiding an aerosol-generating substrate; a heating component arranged on the liquid guiding member and for atomizing, when energized, the aerosol-generating substrate; and an electrode lead electrically connected to the heating component and fixing the heating component to the liquid guiding member.

Abstract: A method for time synchronization, includes: acquiring target information including preset mode information; determining a target mode according to the preset mode information; determining a first synchronous clock as a clock source, in the target mode; and generating a first control instruction for controlling a device waiting for the time synchronization to perform the time synchronization according to the first synchronous clock.

Abstract: A method and device for sidelink communication are disclosed. The method is performed by a first terminal, and includes: receiving a sidelink communication resource scheduled by a network device; and sending indication information configured to indicate a use condition of the sidelink communication resource.

Abstract: Embodiments of the present invention disclose a contract management method, apparatus, and system. The method includes: A communication device sends a registration request to a management network element. The registration request includes service request information, and the service request information indicates a specific service. After receiving the registration request from the communication device, the management network element determines a first smart contract based on the service request information in the registration request. Then, the management network element sends the first smart contract to the communication device. According to embodiments of the present invention, service waiting time of a user may be reduced.

Abstract: Ceria particles contain molybdenum. In the ceria particles, the molybdenum may be unevenly distributed in a surface layer of the ceria particles. A crystallite diameter of a [100] plane of the ceria particles may be 250 nm or more. A crystallite diameter of a [101] plane of the ceria particles may be 300 nm or more. A median diameter D50 of the ceria particles calculated by a laser diffraction/scattering method may be 5.00 ?m or more and 1000.00 ?m or less. A method for producing the ceria particles includes calcining a cerium compound in presence of a molybdenum compound. The molybdenum compound may be at least one compound selected from a group including molybdenum trioxide, lithium molybdate, potassium molybdate and sodium molybdate. In the method for producing the ceria particles, a calcination temperature may be 800° C. or higher and 1600° C. or lower.

Abstract: A ceria-carbon-sulfur (CeO2—C—S) composite including a ceria-carbon (CeO2—C) composite in which cylindrical carbon materials having ceria (CeO2) particles bonded to surfaces thereof are entangled and interconnected to each other in three dimensions; and sulfur introduced into at least a portion of an outer surface and an inside of the ceria-carbon composite, a method for preparing the same, and positive electrode for a lithium-sulfur battery and a lithium-sulfur battery including the same.

Abstract: An exemplary system according to the present disclosure comprises a computing device that in operation, causes the system to receive financial product or financial portfolio data, map the financial product to a risk factor, execute a risk factor simulation process involving the risk factor, generate product profit and loss values for the financial product or portfolio profit and loss values for the financial portfolio based on the risk factor simulation process, and determine an initial margin for the financial product. The risk factor simulation process can be a filtered historical simulation process.

Abstract: The embodiments of the present disclosure provide a method for vascular analysis. The method may include determining a peak phase in a plurality of phases based on perfusion scanning data of the plurality of phases; obtaining a reconstruction result of the peak phase by performing, based on the perfusion scanning data of the peak phase, image reconstruction; and performing vascular analysis based on the reconstruction result of peak phase.

Abstract: An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor.

Abstract: A cell alignment metric detection method, a controller, a detection system and a storage medium are disclosed. The cell alignment metric detection method includes: acquiring a first cell image; inputting the first cell image into a first training model for detection processing to obtain a region of interest; obtaining a second cell image and terminal position information of a second electrode plate according to the region of interest and the first cell image; inputting the second cell image into a second training model for separation processing to obtain a third cell image and terminal position information of a first electrode plate; performing image extraction and analysis on the third cell image to obtain a misalignment quantity; and obtaining the cell alignment metric according to the terminal position information of the second electrode plate and the first electrode plate and the misalignment quantity.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.

Abstract: Disclosed is a process method for controlling a glossiness of an electroplated nickel-layer, which comprises: subjecting a metal substrate to pre-treatment, copper plating process, satin-nickel plating process, semi-bright-nickel plating process, and post-treatment in turn. The present application can effectively control the surface glossiness of a nickel-layer by optimizing the process flow of the electroplated nickel-layer and process parameters in the electroplating process, so that the glossiness of the product reaches 290-310 Gu, which fully meets the specification requirements of the product glossiness of 280-350 Gu.

Abstract: A device, system, and method for high-resolution spatial omic detection of a tissue sample are provided, which include a slide with a microwell reaction chamber array capable of accommodating microcarriers, a method for modifying a nucleic acid molecular identifier, and a method for reducing cross pollution of omic information in a process of capturing spatial omic information of a tissue sample, respectively. By using the method for spatial omic detection, the resolution of the spatial omic detection is significantly improved and the detection cost is reduced, and the cross pollution of the spatial omic information is fundamentally reduced.

Abstract: Disclosed are electrochemical-mechanical thinning method and apparatus for large-diameter semiconductor wafers. The large-diameter semiconductor wafers are thinned by combining anodizing modification and mechanical grinding. The apparatus includes a grinding tool system, a wafer holding device and a grinding wheel dressing device. The grinding tool system includes a base plate and a cup-shaped grinding wheel. The base plate is taken as a cathode, and the semiconductor wafer is taken as an anode. During thinning, both the cathode and the anode are immersed in an electrolyte. Under the action of an external electric field, the semiconductor wafer is subjected to surface modification and softening. At the same time, an oxide layer and intermediate state products generated by modification are removed together by using the grinding wheel, and the semiconductor wafer is thinned under the combined action of multi-energy fields of electricity, chemistry, machinery and force.