Abstract: A prosthetic heart valve configured to replace a native heart valve and having a support frame configured to be reshaped into an expanded form in order to receive and/or support an expandable prosthetic heart valve therein is disclosed, together with methods of using same. The prosthetic heart valve may be configured to have a generally rigid and/or expansion-resistant configuration when initially implanted to replace a native valve (or other prosthetic heart valve), but to assume a generally expanded form when subjected to an outward force such as that provided by a dilation balloon or other mechanical expander.

Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.

Abstract: A method of forming a semiconductor device includes forming a photoresist layer over a mask layer, patterning the photoresist layer, and forming an oxide layer on exposed surfaces of the patterned photoresist layer. The mask layer is patterned using the patterned photoresist layer as a mask. A target layer is patterned using the patterned mask layer as a mask.

Abstract: A cable includes: a pair of core wires; a shielding layer covering the pair of core wires; an insulating outer layer covering the shielding layer; a ground wire between the pair of core wires and the shielding layer; and a filler wire between the pair of core wires and the shielding layer, and the filler wire is arranged symmetrically with the ground wire.

Abstract: A thrombectomy device (100) comprising an aspiration pump (10), a catheter (20) and a valve (30) is provided. The aspiration pump (10) is for providing an negative pressure continuously or by interval. The catheter (20) having a distal end (23), mid portion (22) and a proximal end (21) and defining a longitudinal axis. The valve (30) connects between the aspiration pump (10) and the proximal end (21) of the catheter (20) or connects to the catheter (20). Wherein, the catheter (20) comprises at least one elastic area (24), which is compressed along the longitudinal axis in response to application of the negative pressure and expanded along the longitudinal axis in response to relieve of the negative pressure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a deep trench isolation (DTI), an interconnect structure, and a conductive pillar. The DTI is disposed in the substrate and the interconnect structure is disposed over the substrate. The conductive pillar extends from the interconnect structure toward the substrate and penetrates the DTI. A method of manufacturing the semiconductor structure is also provided.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive element, an active chip, an encapsulation layer, another redistribution layer, and a conductive terminal. The conductive element, the active chip, and the encapsulation layer are disposed on the redistribution layer and the encapsulation layer surrounds the conductive element and the active chip. The another redistribution layer is disposed on the conductive element, the active chip and the encapsulation layer and electrically connected to the redistribution layer through the conductive element.

Abstract: A hand-held scanning probe is included in an optical scanning system. The hand-held scanning probe includes a housing and an optical component. The optical component includes a first lens, a reflector, a two-dimensional beam scanning mechanism, a splitter and a second lens. The first lens is used to receive a laser beam split by a fiber-coupled splitter and convert the laser beam into a form of collimated light. The reflector is used to refract the laser beam. The two-dimensional beam scanning mechanism provides the laser beam to a surface for two-dimensional scanning, producing a swing beam. The splitter is used to separate a scanning end beam returned from the test specimen from an illumination beam into two different light paths. The second lens is used to focus the swing beam at the test surface to form the scanning end beam for scanning. An optical scanning system is also provided.

Abstract: The present invention provides a contrast agent which is efficiently and specifically absorbed by tumor cells, suitable for use in single photon emission computed tomography for the diagnosis, efficacy assessment and tumor tracking of neuroblastoma, pheochromocytoma or congestive heart failure.

Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: Disclosed herein is a recombinant antibody exhibiting binding affinity and/or neutralizing activity to porcine epidemic diarrhea virus (PEDV). According to some embodiments of the present disclosure, the PEDV is genotype 1 (G1) or genotype 2b (G2b) PEDV. Also disclosed herein are methods of diagnosing and treating PEDV infection by use of the present recombinant antibody.

Abstract: A chip structure has a chip body having a plurality of pads, a plurality of metal bumps respectively formed on the pads, and a patterned bump directly formed on the chip body. The patterned bump has at least two different upper and lower plane patterns. A top surface of each of the metal bumps is higher than a height position on which the upper plane pattern is. When the chip structure is ground to the height position, the ground tops of the metal bumps and the upper plane pattern are flush. Therefore, detecting whether the upper plane pattern is exposed determines whether all the metal bumps are exposed and flush to each other to avoid insufficient grinding depth or over-ground.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a plurality of micro-lens chips arranged at intervals and a coplanar control layer. The coplanar control layer is configured to encapsulate the plurality of micro-lens chips therein. At least one surface of each of the micro-lens chips is exposed outside the coplanar control layer, and the at least one surface of each of the micro-lens chips is coplanar.

Abstract: An electronic device includes a substrate and a light shielding layer. The light shielding layer is arranged on the substrate. The light shielding layer has an edge, a main body area, and a peripheral area between the edge and the main body area, wherein a light penetration rate of the light shielding layer in the peripheral area is greater than a light penetration rate of the light shielding layer in the main body area.

Abstract: A cable includes: a pair of inner conductors; a respective first insulating layer extruded on each of the pair of inner conductors; a second insulating layer covering the first insulating layers; a shielding layer covering the second insulating layer; and an outer coating layer covering the shielding layer, wherein the second insulating layer is a braided layer.

Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes a first package and a second package, and the second package is disposed on the first package. The first package includes a first redistribution layer, at least one chip and a second redistribution layer. The chip is disposed between the first redistribution layer and the second redistribution layer. The second package includes a third redistribution layer and at least three light-emitting elements. The third redistribution layer is electrically connected to the second redistribution layer, and the second redistribution layer is disposed between the chip and the third redistribution layer. The light-emitting elements are disposed on the third redistribution layer and electrically connected to the third redistribution layer. Each light-emitting element includes a first surface opposite to the third redistribution layer, and the first surfaces of the light-emitting elements are coplanar.

Abstract: An overlay mark includes a first feature extending in an X-direction, wherein the first feature is a first distance from a substrate. The overlay mark further includes a second feature extending in a Y-direction perpendicular to the X-direction, wherein the second feature is a second distance from the substrate, and the second distance is different from the first distance, wherein at least one of the first feature or the second feature comprises a conductive material. The overlay mark further includes a third feature extending in the X-direction and the Y-direction, wherein the third feature is a third distance from the substrate, and the third distance is different from the first distance and the second distance. The first distance, the second distance and the third distance from the substrate are along a Z-direction perpendicular to both the X-direction and the Y-direction.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Abstract: A wafer-level full-color display device and a method for manufacturing the same are provided. In the method, a plurality of LED structures arranged into an array and a peripheral electrode layer surrounding the LED structures are formed on a front side of a wafer substrate. Next, one or more insulating layers are formed to flatten the stepped difference of each of the LED structures and fill up the height difference between the LED structures and the wafer substrate. Afterwards, conductive lines are formed on the one or more insulating layers to provide a reliable electrical connection between the LED structures and the peripheral electrode layer.