Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.

Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

Abstract: Disclosed herein are compounds having a structure according to Formula I, and compositions containing those compounds. Methods of preparing the compounds, and methods of using the compounds for the treatment of diseases, disorders, or conditions are also described.

Abstract: An integrated circuit structure and method of manufacturing the same are provided. The integrated circuit structure includes a plurality of conductive features within a dielectric layer overlying a substrate, a barrier layer disposed between each of the plurality of the conductive features and the dielectric layer, a protection layer between sidewalls of the barrier layer and the dielectric layer and a void disposed within the dielectric layer at a position between two adjacent conductive features of the plurality of the conductive features.

Abstract: Disclosed is an image display format conversion method, comprising: a frame recognition step of performing a frame recognition process on a comic page image to obtain a plurality of comic frame images and frame position information; a frame sequence determination step of determining a frame viewing sequence according to a selected regional layout rule; and a frame reassembly step of reassembling and converting, based on the frame viewing sequence, the plurality of comic frame images into a digital media in an animation-like format or a scrolling-comic format.

Abstract: The present disclosure provides an operation method of a PET (positron emission tomography) quantitative localization system, which includes steps as follows. The PET image and the MRI (magnetic resonance imaging) of the patient are acquired; the nonlinear deformation is performed on the MRI and the T1 template to generate deformation information parameters; the AAL (automated anatomical labeling) atlas is deformed to an individual brain space of the patient, so as to generate an individual brain space AAL atlas, where the AAL atlas and the T1 template are in a same space; lateralization indexes of the ROIs of the individual brain space AAL atlas corresponding to the PET image normalized through the gray-scale intensity are calculated; the lateralization indexes are inputted into one or more machine learning models to analyze the result of determining a target.

Abstract: Disclosed herein are compounds that are Cbl-b inhibitors having a structure according to Formula I, and compositions containing those compounds. Methods of preparing the compounds, and methods of using the compounds for the treatment of diseases, disorders, or conditions are also described.

Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.

Abstract: A method of manufacturing colorful thermal insulation films is provided. A substrate is connected with a metal adhesion layer and then the metal adhesion layer is connected with a porous anodic aluminum oxide (AAO) layer. A porosity of the AAO layer is changed by pore-widening. Thereby the thermal insulation film produced shows the color by the structure color of the AAO layer. Thus no dyes and organic compounds are required to be added during manufacturing process and environmental pollution caused by these substances can be avoided. The pore-widening changes the porosity of the AAO layer and further provides convenient color adjustment so that the colorful thermal insulation film with different colors can be produced easily. Besides providing attractive appearance, the colorful thermal insulation film filters out light with specific wavelengths.

Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.

Abstract: A patterning process that can be utilized in order to help form conductive lines within a dielectric layer of a metallization layer is provided. In an embodiment a first interfacial layer is patterned a first time, the first interfacial layer being located over a first hard mask layer over a dielectric layer, the patterning the first interfacial layer the first time forming a first opening, which is filled with a first dielectric material. The first interfacial layer is patterned a second time, the patterning the first interfacial layer the second time forming second openings in the first interfacial layer, at least one of the second openings exposing the first dielectric material. The first dielectric material is removed, and the dielectric layer is patterned a second time after the removing the first dielectric material using the first interfacial layer as a mask, the patterning the dielectric layer extending the second openings.

Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.

Abstract: A memory device includes a plurality of computing memory cells, each of which stores a weight value, receives an input value and generates an output value. Each of the computing memory cells includes a transistor connected to a bit line and a word line, receiving a sensing current through the bit line and receiving an input voltage through the word line. When the sensing current flows through the transistor, the computing memory cell generates a first voltage difference corresponding to the output value. The output value is equal to a product of the input value and the weight value.

Abstract: The methods and systems provide an ensemble approach that combines multiple single-model-solutions to produce optimal forward-looking forecasts. Moreover, the methods and systems provide an architecture for this ensemble approach that ensures that the limitations for individual ensemble model components are compensated by other ensemble model components as inputs and outputs from ensemble model components are fed from one ensemble model component to another in a specific order to generate a final output upon which a conservative prediction is based.

Abstract: A memory device for performing an in-memory computation, comprising a plurality of memory cells each stores a weight value and comprises a transistor and a resistor. A gate of the transistor receives an input voltage, the input voltage indicates an input value. When the transistor operates at a first operating point, the input voltage is equal to a first input voltage, when the transistor operates at a second operating point, the input voltage is equal to a second input voltage. The resistor is connected to a drain and a source of the transistor, when the resistor operates in a first state, the weight value is equal to a first weight value, when the resistor operates in a second state, the weight value is equal to a second weight value. Each of the memory cells performs a product computation of the input value and the weight value.

Abstract: An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

Abstract: The present disclosure provides compositions and methods for controlled release of macromolecules (such as proteins and polypeptides). The present disclosure also provides method for preparing and using the same.

Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.