Abstract: A key manager according to one embodiment is connected to a QKD device generating a link key by QKD, an application of a user network, and a QKDN control device. The key manager includes a communication interface and a processor. The communication interface receives, from the QKDN control device, route information for transmitting an application key to a destination key manager. The processor identifies, from the route information, a key manager that is located in a first key sharing network to which the key manager connected to the application belongs and is connected to a second key sharing network. The processor determines a route in the first key sharing network from resource information of the first key sharing network, and causes the communication interface to transmit the application key encrypted with the link key by using the route.

Abstract: The present disclosure provides compositions comprising one or more polymers capable of forming a hydrogel and methods for making and using the same. More specifically, the present disclosure provides compositions comprising one or more polymers capable of forming a hydrogel with prolonged mucosal retention, and methods for making and using the same.

Abstract: A key manager according to one embodiment is connected to a QKD device generating a link key by QKD. The key manager includes a communication interface and a processor. The communication interface receives, from a source application of a user network, information for identifying the source application, information for identifying a destination application, and a requested amount of an application key used for encrypting or decrypting communication in the user network. The processor identifies a key manager as a sharing destination of the application key and determines a sharing amount. The processor causes the communication interface to transmit the application key to the key manager as the sharing destination. The application key to be transmitted has been encrypted by using the link key and satisfies the sharing amount. The processor causes the communication interface to transmit the application key of the requested amount to the source application.

Abstract: A neural network computing method and a neural network computing device are provided. The neural network computing method includes the following steps. At least one chosen layer is decided. A plurality of front layers previous to the chosen layer are decided. A selected element is selected from a plurality of chosen elements in the chosen layer. A front computing data group related to the selected element is defined. The front computing data group is composed of only part of a plurality of front elements in the front layers. The selected element is computed according to the at least one front computing data group.

Abstract: A method of predicting the efficacy of natural killer cells, including: generating a plurality of training data corresponding to a plurality of donors based on a characteristic factor and a corresponding killing result against the target cancer cells of a plurality of cultured natural killer cells from the donors; obtaining a trained neural network model by inputting the plurality of training data into a neural network model; inputting a to-be-tested input vector corresponding to at least one characteristic factor of a to-be-tested natural killer cell into the trained neural network model to obtain an outputted result vector of the trained neural network model, wherein the result vector indicates a predicted killing result corresponding to the target cancer cell after applying the to-be-tested natural killer cell; and determining a quality of the to-be-tested natural killer cell based on the predicted killing result.

Abstract: A cultivation method for drip irrigation of cotton fields in saline-alkali soil is provided, belonging to the field of agricultural planting technologies. It mainly includes performing land preparation; setting a planting mode; laying tubes; performing a high frequency drip irrigation; fertilizing with water; performing intertillage; performing chemical control; and performing green prevention and control.

Abstract: The disclosure provides a cache device, which includes: a first transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node; an inverter having an input terminal and an output terminal, in which the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is configured to output a read voltage.

Abstract: A method of manufacturing colorful thermal insulation films is provided. A substrate is connected with a metal adhesion layer and then the metal adhesion layer is connected with a porous anodic aluminum oxide (AAO) layer. A porosity of the AAO layer is changed by pore-widening. Thereby the thermal insulation film produced shows the color by the structure color of the AAO layer. Thus no dyes and organic compounds are required to be added during manufacturing process and environmental pollution caused by these substances can be avoided. The pore-widening changes the porosity of the AAO layer and further provides convenient color adjustment so that the colorful thermal insulation film with different colors can be produced easily. Besides providing attractive appearance, the colorful thermal insulation film filters out light with specific wavelengths.

Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

Abstract: A method includes patterning a mandrel layer over a target layer to form first mandrels and second mandrels, the first mandrels having a larger width than the second mandrels. A spacer layer is formed over the first mandrels and the second mandrels, and altered so that a thickness of the spacer layer over the first mandrels is greater than a thickness of the spacer layer over the second mandrels. Spacers are formed from the spacer layer which have a greater width adjacent the first mandrels than the spacers which are adjacent the second mandrels. The spacers are used to etch a target layer.

Abstract: The present invention discloses an image processing method. The image processing method includes the following steps: (a), a to-be-processed image is corrected as a first correction image according to a first mapping relationship along a correction direction; (b) the first correction image by an angle is rotated; and (c) the rotated first correction image is corrected as a second correction image according to a second mapping relationship along the same correction direction. In embodiment, given that the to-be-processed image is deformed along two different directions, the to-be-processed image is corrected along the same correction direction, such that correction complexity could be reduced.

Abstract: An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.

Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.

Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

Abstract: A semiconductor device includes a resistor. The resistor includes two bottom electrodes adjacent to each other, a resistive layer, a top electrode and a conductive sidewall. The resistive layer is disposed on the two bottom electrodes. The top electrode is disposed on the resistive layer. The conductive sidewall surrounds the top electrode and is electrically connected to the top electrode and a bottom electrode of the two bottom electrodes. The top electrode overlaps the two bottom electrodes in the first direction, and extends above the two bottom electrodes along a second direction different from the first direction.

Abstract: A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.

Abstract: A memory device and an operation method thereof for performing a multiply-accumulate operation are provided. The memory device includes at least one memory string, a plurality of data lines and a string line. The memory string includes a plurality of unit cells having a plurality of stored values. The data lines are respectively connected to the unit cells to receive a plurality of data signals having a plurality of inputting values. When the data signals are inputted into the unit cells, a plurality of nodes among the unit cells are kept at identical voltages. The string line is connected to the memory string to receive a sensing signal and obtain a measured value representing a sum-of-product result of the inputting values and the stored values. The data signals and the sensing signal are received at different time.

Abstract: A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing at least one checking operation to obtain at least one checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device, wherein the L2P table includes address mapping information for accessing the target data, and performing the at least one checking operation to obtain at least one checking result includes checking whether a first L2P-table index pointing toward the L2P table and a second L2P-table index sent from the host device are equivalent to each other; and reading the target data from the NV memory, and sending the target data to the host device.

Abstract: The present disclosure provides compositions comprising one or more polymers capable of forming a hydrogel and methods for making and using the same. More specifically, the present disclosure provides compositions comprising one or more polymers capable of forming a hydrogel with prolonged mucosal retention, and methods for making and using the same.

Abstract: An in-memory computing (IMC) memory device and an IMC method are provided. The IMC memory device includes: a plurality of memory cells, the memory cells forming a plurality of computing layers; and a plurality of computing layer connectors, the computing layer connectors connecting between the computing layers. A first computing layer input is inputted into a first computing layer of the computing layers. The first computing layer generates a first computing layer output. A first computing layer connector of the computing layer connectors converts the first computing layer output into a second computing layer input. The first computing layer connector inputs the second computing layer input into a second computing layer of the computing layers. The computing layer connectors are a plurality of inverters, a plurality of voltage-to-voltage converters or a plurality of current-to-voltage converters.