Abstract: Circuitry coupled to a programmable element comprising metal oxide is configured to execute a program-verify operation including: an initial cycle of a program operation and a verify operation, and subsequent cycles. The initial cycle includes an initial instance of the program operation to establish a cell resistance of the programmable element, and an initial instance of the verify operation to determine whether the cell resistance of the memory cell is within the target resistance range. At least one of the subsequent cycles includes an additional pulse having a second polarity to the programmable element, and a subsequent instance of the verify operation. The first polarity of the initial program pulse and the second polarity of the additional pulse have opposite polarities. A subsequent instance of the program operation includes applying a subsequent program pulse having the first polarity to the programmable element.

Abstract: A memory structure including an insulating layer, a first electrode layer and a first barrier is provided. The insulating layer has a recess. The first electrode layer is formed in the recess and has a first top surface. The first barrier is formed between the insulating layer and the first electrode layer, and has a second top surface lower than the first top surface. The first top surface and the second top surface are lower than an opening of the recess.

Abstract: An antenna including an antenna structure disposed on a substrate is provided. The antenna structure includes a first radiation part, a second radiation part, a metal coupling part, a third radiation part and a feeding point. The first radiation part has a first bend, a second bend and an opening end. The first radiation part extends from a grounding point of a grounding plane and the opening end thereof is nearing the grounding plane. The second radiation part extends from a section between the first bend of the first radiation part and the grounding point. The metal coupling part is nearing the first radiation part and the second radiation part. The third radiation part is disposed between the second radiation part and the grounding plane, and extends from the metal coupling part. The feeding point is coupled to where the third radiation part and the metal coupling part connected.

Abstract: The present invention relates to metal oxide based memory devices and methods for manufacturing such devices, and more particularly to memory devices having data storage materials based on metal oxide compounds fabricated with a biased plasma oxidation process which improves the interface between the memory element and a top electrode for a more a uniform electrical field during operation, which improves device reliability.

Abstract: A cycling computer with image processing device is provided for a bike and includes a monitor and a button. The cycling computer is designed to record traffic conditions and physiological signals of a rider. The traffic conditions and the physiological signals are digitalized into cycling data to be displayed on a monitor through operation of a button. A CCD device is mounted on the cycling computer for recording environmental images. An image processing unit is connected to the CCD device for receiving the environmental images captured by the CCD module. The environmental images are incorporated with the cycling data to form a plurality of object images. The object images are displayed on the monitor for versatile applications to the rider.

Abstract: Circuitry coupled to a programmable element comprising metal oxide is configured to execute a program-verify operation including: an initial cycle of a program operation and a verify operation, and subsequent cycles. The initial cycle includes an initial instance of the program operation to establish a cell resistance of the programmable element, and an initial instance of the verify operation to determine whether the cell resistance of the memory cell is within the target resistance range. At least one of the subsequent cycles includes an additional pulse having a second polarity to the programmable element, and a subsequent instance of the verify operation. The first polarity of the initial program pulse and the second polarity of the additional pulse have opposite polarities. A subsequent instance of the program operation includes applying a subsequent program pulse having the first polarity to the programmable element.

Abstract: A multi-phase boost converter with phase self-detection and a detecting circuit thereof are provided. The multi-phase boost converter comprises M switching circuits, a capacitor, a control circuit and a detecting circuit. Each switching circuit has an input end and an output end. N inductors are coupled in parallel between the input ends and an input voltage. The output ends are coupled to an output voltage. The control circuit controls the conduction status of the switching circuits according to a feedback voltage corresponding to the output voltage. The detecting circuit coupled between the input ends and the control circuit detects the conduction status between the input voltage and each of the input ends, for outputting a first control signal. The control circuit controlled by the first control signal selectively controls at least one of the switching circuits. N is a positive integer less than or equal to M.

Abstract: A fingerprint detection apparatus, a mobile device using the same and a manufacturing method thereof are provided. The fingerprint detection apparatus comprises an image sensing integrated circuit and a spatial filter disposed on the image sensing integrated circuit. The spatial filter has adjacent light tunnels for restricting an incident angle of light to the image sensing integrated circuit to prevent scattered light from entering the image sensing integrated circuit.

Abstract: A blue light leakage-suppressing LED structure for emitting white light includes at least one LED chip, an encapsulation element, a light output lens, and an optical fuse coating formed of a thermosensitive material; or includes at least one LED chip and an encapsulation element formed of a mixture of an encapsulation material and a thermosensitive material; or includes at least one blue LED chip, a fluorescent powder layer, an isolation region, an optical fuse layer, and a light output lens. Thanks to the hue changing property of the thermosensitive material, the LED structure can reduce the intensity of its short-wavelength light component and its overall brightness significantly before reaching the L70 threshold, after passing which the LED structure will emit excessive blue light. Thus, the user is protected from overexposure to blue light and will be reminded to replace the LED structure when the LED structure is about to malfunction.

Abstract: A technique for setting network communications for a computer host having multiple network interface controllers (NICs) includes performing network communication for a baseboard management controller (BMC) using a first NIC. In response to actuation of a switch of a network connector jack that is associated with the first NIC, a switching signal is sent from the switch to the BMC. In response to receipt of the switching signal at the BMC, network communication for the BMC is performed using a second NIC.

Abstract: A memory device comprises a substrate, a first electrode layer, a spacer, a memory layer and a second electrode layer. The substrate has a recess. The first electrode layer is formed in the recess and has a top surface exposed from an opening of the recess. The spacer covers on a portion of the top surface, so as to define a contact area on the top surface. The memory layer is formed on the contact area. The second electrode layer is formed on the memory layer and electrically connected to the memory layer.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises an access device, a dielectric layer, a barrier layer, a first interlayer conductor, a first barrier liner, a second interlayer conductor, a second barrier liner, a memory element and a top electrode layer. The access device has two terminals. The dielectric layer covers the access device. The barrier layer is disposed on the dielectric layer. The first and second interlayer conductors are connected to the two terminals, respectively. The first and second barrier liners are disposed on sidewalls of the first and second interlayer conductors, respectively. The memory element is disposed on the first interlayer conductor. The top electrode layer is disposed on the barrier layer and the memory element and covers the memory element.

Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

Abstract: A composition including algal oil body(ies), a modified algal oil body, a method for stabilizing an algal oil body, and a method for improving the oxidation resistance of an algal oil body and/or preventing oil leakage of an algal oil body are disclosed. Specifically, a modified algal oil body including an algal of body, a phospholipid and an of body protein, a method for improving the stability of an algal oil body by adding an oil body protein and a phospholipid into the algal oil body, and a method for improving oxidation resistance of an algal oil body by adding thereinto an oil body protein are disclosed.

Abstract: In accordance with an embodiment, a method comprises providing a substrate having a conductive material thereon, forming a ground plane, a first trace rail, and a first perpendicular trace from the conductive material, and forming an insulator material over the ground plane, the first trace rail, and the first perpendicular trace. The ground plane is between the first trace rail and an area of the substrate over which will be a die. The first trace rail extends along a first outer edge of the ground plane, and the first perpendicular trace is coupled to the first trace rail and extends perpendicularly from the first trace rail.

Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

Abstract: A multi-phase boost converter with phase self-detection and a detecting circuit thereof are provided. The multi-phase boost converter comprises M switching circuits, a capacitor, a control circuit and a detecting circuit. Each switching circuit has an input end and an output end. N inductors are coupled in parallel between the input ends and an input voltage. The output ends are coupled to an output voltage. The control circuit controls the conduction status of the switching circuits according to a feedback voltage corresponding to the output voltage. The detecting circuit coupled between the input ends and the control circuit detects the conduction status between the input voltage and each of the input ends, for outputting a first control signal. The control circuit controlled by the first control signal selectively controls at least one of the switching circuits. N is a positive integer less than or equal to M.

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.

Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

Abstract: A memory device comprises a substrate, a first electrode layer, a spacer, a memory layer and a second electrode layer. The substrate has a recess. The first electrode layer is formed in the recess and has a top surface exposed from an opening of the recess. The spacer covers on a portion of the top surface, so as to define a contact area on the top surface. The memory layer is formed on the contact area. The second electrode layer is formed on the memory layer and electrically connected to the memory layer.