Patents by Inventor Anand Gupta

Anand Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160299881
    Abstract: The disclosed embodiments illustrate methods and systems for summarizing an electronic document. The method includes extracting, by a natural language processor, one or more sentences from said electronic document. The method further includes creating a graph, comprising one or more nodes and one or more edges connecting said one or more nodes, each node being representative of a sentence. An edge is placed between a pair of sentences based on a threshold value and a first score. The first score corresponds to a measure of an entailment between said pair of sentences. Thereafter, the method includes identifying a set of nodes from said one or more nodes by applying a minimum vertex cover algorithm on said graph. The sentences associated with said identified set of nodes are utilizable to create a summary of said electronic document. The method is performed by one or more microprocessors.
    Type: Application
    Filed: April 7, 2015
    Publication date: October 13, 2016
    Inventors: Anand Gupta, Manpreet Kaur, Shachar Mirkin
  • Patent number: 9040816
    Abstract: Methods of forming a photovoltaic structures including nanoparticles are disclosed. The method includes electrospray deposition of nanoparticles. The nanoparticles can include TiO2 nanoparticles and quantum dots. In an example, the nanoparticles are formed on a flexible substrate. In various examples, the flexible substrate is light transparent. Photovoltaic structures and apparatus for forming photovoltaic structures are disclosed.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: May 26, 2015
    Assignee: Nanocopoeia, Inc.
    Inventor: Anand Gupta
  • Patent number: 8624857
    Abstract: A method for generating a desired haptics effect is provided. A haptics effect instruction is generated by a host processor responsive to a touch screen, where the haptics effect instruction corresponds to the desired haptics effect. This haptics effect instruction is received by a haptics driver, and a haptic profile from the haptics effect instruction is generated from the haptics effect instruction. The haptic profile includes at least one of a profile word, a move word, wait/halt word, and a branch word, and a sine wave is generated from the from the haptic profile that corresponds to the desired haptics effect.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: January 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Hugo Cheung, Anand Gupta
  • Publication number: 20120200509
    Abstract: A method for generating a desired haptics effect is provided. A haptics effect instruction is generated by a host processor responsive to a touch screen, where the haptics effect instruction corresponds to the desired haptics effect. This haptics effect instruction is received by a haptics driver, and a haptic profile from the haptics effect instruction is generated from the haptics effect instruction. The haptic profile includes at least one of a profile word, a move word, wait/halt word, and a branch word, and a sine wave is generated from the from the haptic profile that corresponds to the desired haptics effect.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 9, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Hugo Cheung, Anand Gupta
  • Publication number: 20080210302
    Abstract: Methods of forming a photovoltaic structures including nanoparticles are disclosed. The method includes electrospray deposition of nanoparticles. The nanoparticles can include TiO2 nanoparticles and quantum dots. In an example, the nanoparticles are formed on a flexible substrate. In various examples, the flexible substrate is light transparent. Photovoltaic structures and apparatus for forming photovoltaic structures are disclosed.
    Type: Application
    Filed: December 10, 2007
    Publication date: September 4, 2008
    Inventor: Anand Gupta
  • Patent number: 6809809
    Abstract: An optical inspection module is provided for detecting defects on a substrate having first and second opposite planar surfaces. The module includes a substrate holding position and first and second measurement instruments. The first instrument includes a first illumination path extending to the substrate holding position and having a grazing angle of incidence with the first surface, which illuminates substantially the entire first surface. A first optical element is oriented to collect non-specularly reflected light scattered by the first surface. A first photodetector has a plurality of pixels positioned within a focal plane of the first lens, which together form a field of view that covers substantially the entire first surface. The second instrument includes a sensor oriented for sensing a physical characteristic of the second surface when the substrate is held in the substrate holding position and the first surface is being illuminated.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: October 26, 2004
    Assignee: Real Time Metrology, Inc.
    Inventors: Patrick D. Kinney, Anand Gupta, Nagaraja P. Rao
  • Publication number: 20040012775
    Abstract: An optical inspection module is provided for detecting defects on a substrate having first and second opposite planar surfaces. The module includes a substrate holding position and first and second measurement instruments. The first instrument includes a first illumination path extending to the substrate holding position and having a grazing angle of incidence with the first surface, which illuminates substantially the entire first surface. A first optical element is oriented to collect non-specularly reflected light scattered by the first surface. A first photodetector has a plurality of pixels positioned within a focal plane of the first lens, which together form a field of view that covers substantially the entire first surface. The second instrument includes a sensor oriented for sensing a physical characteristic of the second surface when the substrate is held in the substrate holding position and the first surface is being illuminated.
    Type: Application
    Filed: March 4, 2003
    Publication date: January 22, 2004
    Inventors: Patrick D. Kinney, Anand Gupta, Nagaraja P. Rao
  • Patent number: 6638886
    Abstract: A plasma fluorine resistant polycrystalline alumina ceramic material is produced by forming a green body including alumina and a binder, and sintering the green body for a time from about 8 to 12 hours. The area % of unsintered particles in the polycrystalline alumina ceramic material does not exceed 0.1 area %, resulting in reduced emission of particles from the material after exposure to plasma fluorine.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: October 28, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Tirunelveli S. Ravi
  • Patent number: 6465043
    Abstract: A method and apparatus for reducing particle contamination in a substrate processing chamber during deposition of a film having at least two layers. The method of the present invention includes the steps of introducing a first process gas into a chamber to deposit a first layer of the film over a wafer at a first selected pressure, introducing a second process gas into the chamber to deposit a second layer of the film over the wafer, and between deposition of said first and second layers, maintaining pressure within the chamber at a pressure that is sufficiently high that particles dislodged by introduction of the second process do not impact the wafer.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: October 15, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Anand Gupta
  • Patent number: 6449521
    Abstract: A method and apparatus for reducing fluorine and other sorbable contaminants in plasma reactor used in chemical vapor deposition process such as the deposition of silicon oxide layer by the reaction of TEOS and oxygen. According to the method of the present invention, plasma of an inert gas is maintained in plasma reactor following chamber clean to remove sorbable contaminants such as fluorine. The plasma clean is typically followed by seasoning of the reactor to block or retard remaining contaminants. According to one embodiment of the invention, the combination of chamber clean, plasma clean, and season film is conducted before PECVD oxide layer is deposited on wafer positioned in the plasma reactor.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: September 10, 2002
    Assignee: Applied Materials, Inc.
    Inventor: Anand Gupta
  • Patent number: 6374770
    Abstract: A chemical vapor deposition system that includes a housing configured to form a processing chamber, a substrate holder configured to hold a substrate within the processing chamber, a gas distribution system configured to introduce gases into the processing chamber, a plasma generation system configured to form a plasma within the processing chamber, a processor operatively coupled to control the gas distribution system and the plasma generation system, and a computer-readable memory coupled to the processor that stores a computer-readable program which directs the operation of the chemical vapor deposition system.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: April 23, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Peter W. Lee, Stuardo Robles, Anand Gupta, Virendra V. S. Rana, Amrita Verma
  • Patent number: 6289843
    Abstract: A method and apparatus for depositing a layer having improved film quality at an interface. The method includes the steps of introducing an inert gas into a processing chamber and forming a plasma from the inert gas by applying RF power to the chamber at a selected rate of increase. After RF power has reached full power, a process gas including a reactant gas is introduced to deposit the layer. In a preferred embodiment, the reactant gas is tetraethoxysilane. In another preferred embodiment, the process gas further includes fluorine.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: September 18, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Virendra V. S. Rana, Amrita Verma, Mohan K. Bhan, Sudhakar Subrahmanyam
  • Patent number: 6291028
    Abstract: A method and apparatus for depositing a layer having improved film quality at an interface. The method includes the steps of introducing an inert gas into a processing chamber and forming a plasma from the inert gas by applying RF power to the chamber at a selected rate of increase. After RF power has reached full power, a process gas including a reactant gas is introduced to deposit the layer. In a preferred embodiment, the reactant gas is tetraethoxysilane. In another preferred embodiment, the process gas further includes fluorine.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 18, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Virendra V. S. Rana, Amrita Verma, Mohan K. Bhan, Sudhakar Subrahmanyam
  • Patent number: 6223685
    Abstract: An improved method of reducing the level of contaminants (e.g., fluorine) absorbed in films deposited within a substrate processing chamber. A seasoning layer is deposited within the substrate processing chamber to cover contaminants that may be absorbed within walls or insulation areas of the chamber interior. The deposited seasoning layer is more stable than prior art seasoning layers and is thus less likely to release the absorbed contaminants into the substrate processing chamber during the subsequent deposition of films. In a preferred embodiment, the seasoning layer is formed from a mixed frequency PECVD process in which the low frequency RF signal is supplied at a high power level to increase ion bombardment and enhance film stability. The increased bombardment favors the formation of stable SiF bonds between silicon and fluorine atoms in the lattice structure of the film rather than unstable SiF2 or other bonds. When residual fluorine atoms (e.g.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: May 1, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Mohan Bhan, Sudhakar Subrahmanyam
  • Patent number: 6214160
    Abstract: An electrostatic technique for removing particulate matter from a semiconductor wafer in a plasma processing chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber. During a particulate removal phase of operation, a normally grounded electrode that supports the wafer is temporarily isolated from ground and a bias voltage generator is simultaneously connected to the electrode, supplying sufficient bias voltage to electrostatically launch particulates from the surface of the wafer. A plasma formed above the normally grounded electrode is maintained during the particulate removal phase, and particulates launched from the wafer become suspended in a sheath region surrounding the plasma, from where they can be later removed by a purging flow of gas. Preferably, the bias voltage generator provides a bias voltage that alternates in polarity, to ensure removal of both positively-charged and negatively charged particles from the wafer surface.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: April 10, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Charles Dornfest, Anand Gupta, Gerald Girard
  • Patent number: 6191026
    Abstract: A semiconductor manufacturing process with improved gap fill capabilities is provided by a three step process of FSG deposition/etchback/FSG deposition. A first layer of FSG is partially deposited over a metal layer. An argon sputter etchback step is then carried out to etch out excess deposition material. Finally, a second layer of FSG is deposited to complete the gap fill process.
    Type: Grant
    Filed: January 9, 1996
    Date of Patent: February 20, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Virendra V. S. Rana, Andrew Conners, Anand Gupta, Xin Guo, Soonil Hong
  • Patent number: 6159333
    Abstract: An apparatus for processing substrates that is configured for a cleaning operation by loading a cleaning process wafer onto the susceptor before forming a cleaning plasma in the processing chamber. In one embodiment, a ceramic wafer is chosen to have a dielectric value sufficient to alter the electromagnetic field of the plasma, and spreads the plasma away from the susceptor during a cleaning operation, thus reducing damage to the susceptor. The plasma may be directed towards the walls of the chamber to reduce chamber cleaning time.
    Type: Grant
    Filed: October 8, 1998
    Date of Patent: December 12, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Srihari Ponnekanti, Gana A. Rimple, Laxman Murugesh
  • Patent number: 6139923
    Abstract: A method and apparatus for reducing particle contamination in a substrate processing chamber during deposition of a film having at least two layers. The method of the present invention includes the steps of introducing a first process gas into a chamber to deposit a first layer of the film over a wafer at a first selected pressure, introducing a second process gas into the chamber to deposit a second layer of the film over the wafer, and between deposition of said first and second layers, maintaining pressure within the chamber at a pressure that is sufficiently high that particles dislodged by introduction of the second process do not impact the wafer.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: October 31, 2000
    Assignee: Applied Materials, Inc.
    Inventor: Anand Gupta
  • Patent number: 6125789
    Abstract: A method and apparatus for increasing the sensitivity of an in situ particle monitor. A light scattering technique, preferably using laser light, is employed to monitor particle concentrations within the processing chamber of a plasma-based substrate processing system. Particle concentrations are increased in the light field of the sensor by creating an electric or magnetic field in the processing chamber to concentrate the particles suspended therein.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: October 3, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Vijay Parkhe
  • Patent number: 6125861
    Abstract: The present invention provides an apparatus for cleaning semiconductor workpieces following a Chemical Mechanical Planarization ("CMP") procedure. Initially, a workpiece is scrubbed to remove some of the slurry material and other contaminants on the surfaces of the workpiece. Next, the workpiece is transported into a chemical-etch cleaning station wherein the workpiece is positioned horizontally such that both the upper and lower surfaces are substantially exposed. The workpiece then is immersed in a cleaning solution which is moved around the various surfaces of the workpiece. The workpiece is immersed in the cleaning solution for a sufficient length of time to remove an appropriate layer of oxide, thereby removing contaminants and smoothing micro scratches from the surfaces of the workpiece.
    Type: Grant
    Filed: April 10, 1998
    Date of Patent: October 3, 2000
    Assignee: SpeedFam-IPEC Corporation
    Inventors: Anand Gupta, Chris Karlsrud, Periya Gopalan, Daniel R. Trojan, Jeffrey B. Cunnane, Jon R. MacErnie