Patents by Inventor Anand Gupta

Anand Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6121163
    Abstract: A method and apparatus for depositing a layer having improved film quality at an interface. The method includes the steps of introducing an inert gas into a processing chamber and forming a plasma from the inert gas by applying RF power to the chamber at a selected rate of increase. After RF power has reached full power, a process gas including a reactant gas is introduced to deposit the layer. In a preferred embodiment, the reactant gas is tetraethoxysilane. In another preferred embodiment, the process gas further includes fluorine.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: September 19, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Virendra V. S. Rana, Amrita Verma, Mohan K. Bhan, Sudhakar Subrahmanyam
  • Patent number: 6103601
    Abstract: A fluorine-doped silicate glass (FSG) layer having a low dielectric constant and a method of forming such an insulating layer is described. The FSG layer is treated with a post-treatment step to make the layer resistant to moisture absorption and outgassing of fluorine atoms. In one embodiment, the post-treatment step includes forming a thin, undoped silicate glass layer on top of the FSG layer, and in another embodiment, the stability of the FSG film is increased by a post-treatment plasma step.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: August 15, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Peter W. Lee, Stuardo Robles, Anand Gupta, Virendra V. S. Rana, Amrita Verma
  • Patent number: 6090167
    Abstract: A method and apparatus for improving film stability of a halogen-doped silicon oxide layer. The method includes the step of introducing helium along with the process gas that includes silicon, oxygen and a halogen element. Helium is introduced at an increased rate to stabilize the deposited layer. In a preferred embodiment, the halogen-doped film is a fluorosilicate glass film and TEOS is employed as a source of silicon in the process gas. In still another preferred embodiment, SiF.sub.4 is employed as the fluorine source for the FSG film.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: July 18, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Mohan Krishan Bhan, Sudhakar Subrahmanyam, Anand Gupta, Viren V. S. Rana
  • Patent number: 6083569
    Abstract: A method and apparatus for neutralizing a wafer in a plasma reactor following a deposition process which charges the wafer and hinders removal of the wafer from the plasma reactor. The wafer is exposed to a plasma of a noble gas such as helium to energize the reaction zone. Then a sufficient amount of an inert electronegative gas such as oxygen to neutralize the wafer is introduced into the plasma reactor in the absence of RF power or other gases. The neutralized wafer is readily removed from the plasma chamber.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: July 4, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Majid K. Shahreza
  • Patent number: 6083451
    Abstract: A polycrystalline alumina ceramic material which is resistant to a fluorine-comprising plasma is produced by forming a green body including alumina and a binder, and sintering the green body at a temperature ranging from about 1400.degree. C. to about 1700.degree. C. for a time from about 8 to about 12 hours. The area % of unsintered particles in the polycrystalline alumina ceramic material does not exceed 0.1 area %, resulting in reduced emission of particles from the material after exposure to plasma fluorine.
    Type: Grant
    Filed: April 18, 1995
    Date of Patent: July 4, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Tirunelveli S. Ravi
  • Patent number: 6029369
    Abstract: A spin dryer assembly for drying workpieces such as semiconductor wafers includes a workpiece platform for receiving a workpiece to be dried. A motor is coupled to and spins the platform to effect removal of water and particulates from the workpiece. Gripping fingers are pivotally mounted around the platform and securely grip the workpiece during drying. Spring loaded plungers maintain the gripping fingers in a secured position during drying. A cam ring is vertically movable into and out of contact with the gripping fingers to bias the gripping portions of the fingers outwardly to a release position after drying.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: February 29, 2000
    Assignee: SpeedFam-IPEC Corporation
    Inventors: Jose R. Gonzalez-Martin, Arthur Hamer, Anand Gupta
  • Patent number: 6020035
    Abstract: An improved method of reducing the level of contaminants (e.g., fluorine) absorbed in films deposited within a substrate processing chamber. A seasoning layer is deposited within the substrate processing chamber to cover contaminants that may be absorbed within walls or insulation areas of the chamber interior. The deposited seasoning layer is more stable than prior art seasoning layers and is thus less likely to release the absorbed contaminants into the substrate processing chamber during the subsequent deposition of films. In a preferred embodiment, the seasoning layer is formed from a mixed frequency PECVD process in which the low frequency RF signal is supplied at a high power level to increase ion bombardment and enhance film stability. The increased bombardment favors the formation of stable SiF bonds between silicon and fluorine atoms in the lattice structure of the film rather than unstable SiF.sub.2 or other bonds. When residual fluorine atoms (e.g.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: February 1, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Mohan Bhan, Sudhakar Subrahmanyam
  • Patent number: 6001728
    Abstract: A method and apparatus for improving film stability of a halogen-doped silicon oxide layer. The method includes the step of introducing helium along with the process gas that includes silicon, oxygen and a halogen element. Helium is introduced at an increased rate to stabilize the deposited layer. In a preferred embodiment, the halogen-doped film is a fluorosilicate glass film and TEOS is employed as a source of silicon in the process gas. In still another preferred embodiment, SiF.sub.4 is employed as the fluorine source for the FSG film.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: December 14, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Mohan Krishan Bhan, Sudhakar Subrahmanyam, Anand Gupta, Viren V. S. Rana
  • Patent number: 5954888
    Abstract: The present invention provides a method for cleaning semiconductor work pieces following a Chemical Mechanical Planarization ("CMP") procedure. Initially, a work piece is scrubbed to remove some of the slurry material and other contaminants on the surfaces of the work piece. Next, the work piece is transported into a HF cleaning station wherein the work piece is positioned horizontally such that both the upper and lower surfaces are substantially exposed. The work piece then is immersed in a hydrogen fluoride ("HF") solution which is circulated around the various surfaces of the work piece. The work piece is immersed in the HF solution for a sufficient length of time to remove an appropriate layer of oxide, thereby removing contaminants and smoothing micro scratches from the surfaces of the work piece.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: September 21, 1999
    Assignee: SpeedFam Corporation
    Inventors: Anand Gupta, Chris Karlsrud, Periya Gopalan
  • Patent number: 5902494
    Abstract: A method and apparatus for preventing particles from dislodging from the interior of a process chamber by preventing DC bias spikes. Such DC bias spikes can be caused by variations in the power or pressure in a process chamber. DC bias spikes are prevented by ramping changes in the pressure at a rate which avoids the creation of such spikes. RF power is ramped down at a rate which avoids spikes.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: May 11, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Stefan Wolff, Maria Galiano
  • Patent number: 5827785
    Abstract: A method and apparatus for improving film stability of a halogen-doped silicon oxide layer. The method includes the step of introducing a process gas including a first halogen source and a second halogen source, different from the first halogen source, into a deposition chamber along with silicon and oxygen sources. A plasma is then formed from the process gas to deposit a halogen-doped layer over a substrate disposed in the chamber. It is believed that the introduction of the additional halogen source enhances the etching effect of the film. The enhanced etching component of the film deposition improves the film's gap-fill capabilities and helps stabilizes the film. In a preferred embodiment, the halogen-doped film is a fluorosilicate glass film, SiF.sub.4 is employed as the first halogen source, TEOS is employed as a source of silicon and the second halogen source is either F.sub.2 or NF.sub.3.
    Type: Grant
    Filed: October 24, 1996
    Date of Patent: October 27, 1998
    Assignee: Applied Materials, Inc.
    Inventors: Mohan Krishan Bhan, Sudhakar Subrahmanyam, Anand Gupta, Virendra V. S. Rana
  • Patent number: 5824375
    Abstract: A method and apparatus for reducing fluorine and other sorbable contaminants in plasma reactor used in chemical vapor deposition process such as the deposition of silicon oxide layer by the reaction of TEOS and oxygen. According to the method of the present invention, plasma of an inert gas is maintained in plasma reactor following chamber clean to remove sorbable contaminants such as fluorine. The plasma clean is typically followed by seasoning of the reactor to block or retard remaining contaminants. According to one embodiment of the invention, the combination of chamber clean, plasma clean, and season film is conducted before PECVD oxide layer is deposited on wafer positioned in the plasma reactor.
    Type: Grant
    Filed: October 24, 1996
    Date of Patent: October 20, 1998
    Assignee: Applied Materials, Inc.
    Inventor: Anand Gupta
  • Patent number: 5810937
    Abstract: A method and apparatus for protecting a susceptor during a cleaning operation by loading a ceramic wafer onto the susceptor before introducing the cleaning agent into the chamber is provided. In particular, the ceramic wafer is chosen to have a dielectric value sufficient to alter the electromagnetic field of a plasma to spread the plasma away from the susceptor during a cleaning operation, directing more of the plasma towards the walls of the chamber.
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: September 22, 1998
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Srihari Ponnekanti, Gana A. Rimple, Laxman Murugesh
  • Patent number: 5779807
    Abstract: An electrostatic technique for removing particulate matter from a semiconductor wafer in a plasma processing chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber. During a particulate removal phase of operation, a normally grounded electrode that supports the wafer is temporarily isolated from ground and a bias voltage generator is simultaneously connected to the electrode, supplying sufficient bias voltage to electrostatically launch particulates from the surface of the wafer. A plasma formed above the normally grounded electrode is maintained during the particulate removal phase, and particulates launched from the wafer become suspended in a sheath region surrounding the plasma, from where they can be later removed by a purging flow of gas. Preferably, the bias voltage generator provides a bias voltage that alternates in polarity, to ensure removal of both positively-charged and negatively charged particles from the wafer surface.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: July 14, 1998
    Assignee: Applied Materials, Inc.
    Inventors: Charles Dornfest, Anand Gupta, Gerald Girard
  • Patent number: 5628870
    Abstract: An apparatus suitable for marking a substrate comprises a holder for holding a substrate and a ground for electrically grounding the substrate. At least one needle electrode has a tip located proximate to the substrate so that there is a gap between the substrate and the tip. A high voltage source provides a current to the electrode tip to ionize the gas in the gap so that the ionized gas can impinge upon and mark the substrate.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: May 13, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Yan Ye, Anand Gupta, Yuri S. Uritsky
  • Patent number: 5622565
    Abstract: The present invention provides an apparatus for semiconductor processing in which the reactor chamber and the vacuum conduit means connected to the chamber are coated with a film of halogenated polymer material having a low vapor pressure and a low sticking coefficient. Preferred materials include low molecular weight polyfluoroethylene polymers such as polytetrafluoroethylene and polychlorotrifluoro-ethylene. A method is provided to prevent contaminant buildup on coated surfaces of semiconductor processing chambers and vacuum conduit means connected thereto during processing of a workpiece.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: April 22, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Yan Ye, Anand Gupta, Shamouil Shamouliam
  • Patent number: 5622595
    Abstract: Contaminant particles in a vacuum plasma processing chamber can be removed from the surface of a substrate in the chamber by first reducing the pressure in the chamber so as to elevate the particles above any obstruction about the substrate, including a clamping ring and the like, maintaining a plasma from a gas fed to the chamber so that the particles are in the plasma, and then increasing the gas flow to the chamber so as to sweep the particles out of the chamber through the exhaust system of the processing chamber while maintaining a plasma in the chamber.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: April 22, 1997
    Assignee: Applied Materials, Inc
    Inventors: Anand Gupta, Joseph Lanucha
  • Patent number: 5608155
    Abstract: The apparent size of sub-micron contaminant particles on a wafer surface is enlarged by selective condensation of a vapor on the particles. The substrate is located proximate to and spaced apart from a liquid vapor source which is heated. The vaporized liquid adheres to the particles, and after a predetermined period of time, condensation of vapor on the substrate is stopped, and the substrate is scanned for detecting the particles.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: March 4, 1997
    Assignee: Applied Materials, Inc.
    Inventors: Yan Ye, Anand Gupta
  • Patent number: 5578131
    Abstract: The present invention provides an apparatus for semiconductor processing in which the reactor chamber and the vacuum conduit means connected to the chamber are coated with a film of halogenated polymer material having a low vapor pressure and a low sticking coefficient. Preferred materials include low molecular weight polyfluoroethylene polymers such as polytetrafluoroethylene and polychlorotrifluoro-ethylene. A method is provided to prevent contaminant buildup on coated surfaces of semiconductor processing chambers and vacuum conduit means connected thereto during processing of a workpiece.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: November 26, 1996
    Inventors: Yan Ye, Anand Gupta, Shamouil Shamouliam
  • Patent number: 5494523
    Abstract: A plasma processing apparatus including a wafer supporting pedestal which is designed to reduce particle trapping phenomena. In a region of the pedestal surface which surrounds or abuts the wafer, the pedestal has a permittivity which is substantially equal to or greater than that of the wafer surface. As a result, the sheath boundary is reshaped to reduce particle trapping.
    Type: Grant
    Filed: February 23, 1995
    Date of Patent: February 27, 1996
    Assignee: Applied Materials, Inc.
    Inventors: Robert J. Steger, Charles S. Rhoades, Anand Gupta