Patents by Inventor Anand Murthy

Anand Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050104160
    Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 19, 2005
    Inventors: Shahriar Ahmed, Ravindra Soman, Anand Murthy, Mark Bohr
  • Publication number: 20050087801
    Abstract: An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.
    Type: Application
    Filed: October 24, 2003
    Publication date: April 28, 2005
    Inventors: Nick Lindert, Anand Murthy, Justin Brask
  • Patent number: 6885084
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: April 26, 2005
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Publication number: 20050079660
    Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.
    Type: Application
    Filed: August 11, 2004
    Publication date: April 14, 2005
    Inventors: Anand Murthy, Boyan Boyanov, Ravindra Soman, Robert Chau
  • Patent number: 6861318
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: March 1, 2005
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Publication number: 20050012146
    Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.
    Type: Application
    Filed: August 12, 2004
    Publication date: January 20, 2005
    Inventors: Anand Murthy, Robert Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan
  • Publication number: 20040253774
    Abstract: There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel.
    Type: Application
    Filed: June 16, 2003
    Publication date: December 16, 2004
    Inventors: Boyan Boyanov, Brian Doyle, Jack T. Kavalieros, Anand Murthy, Robert Chau
  • Publication number: 20040188684
    Abstract: Chemical vapor deposition (CVD) is commonly used to blanket deposit or selectively deposit and grow an epitaxial film on a substrate. When the exposed portion of a substrate's crystalline material is relatively small, however, conventional CVD techniques do not work well and the resulting films are rough and may be unusable. Embodiments of the present invention provide a CVD process for selectively depositing smooth silicon, germanium, or silicon germanium alloy epitaxial films on a substrate's exposed crystalline material when the amount of exposed crystalline material is less than approximately twenty percent.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Glenn A. Glass, Anand Murthy
  • Publication number: 20040192002
    Abstract: A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Ravindra Soman, Anand Murthy, Peter VanDerVoorn, Shahriar Ahmed
  • Patent number: 6797556
    Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: September 28, 2004
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Patrick Morrow
  • Publication number: 20040084735
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Application
    Filed: July 23, 2003
    Publication date: May 6, 2004
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Patent number: 6723622
    Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: April 20, 2004
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Ravindra Soman, Boyan Boyanov
  • Publication number: 20040070035
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Application
    Filed: July 23, 2003
    Publication date: April 15, 2004
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Publication number: 20040048439
    Abstract: A method for forming a base of a bipolar transistor. A narrow base is formed using a flash of boron doping gas in a reaction chamber to create a narrow base with high boron concentration. This method allows for reliable formation of a base with high boron concentration while maintaining manageability in controlling deposition of other materials in a substrate.
    Type: Application
    Filed: August 21, 2002
    Publication date: March 11, 2004
    Inventors: Ravindra Soman, Anand Murthy
  • Patent number: 6703291
    Abstract: The wet etch stage of the salicide process normally used to fabricate polysilicon and silicon-based semiconductor transistors may not be appropriate for germanium-based transistors because the wet etch chemicals at such temperatures will dissolve the germanium leaving no source, gate, or drain for the transistor. In embodiments of the invention, nickel is blanket deposited over the source, drain, and gate regions of the germanium-based transistor, annealed to cause the nickel to react with the germanium, and wet etched to remove un-reacted nickel from dielectric regions (e.g., shallow trench isolation (STI) regions) but leave NiGe in the source, gate, and drain regions. The wet etch is a mild oxidizing solution at room temperature.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 9, 2004
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Steven Keating, Anand Murthy
  • Publication number: 20040007724
    Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.
    Type: Application
    Filed: July 12, 2002
    Publication date: January 15, 2004
    Inventors: Anand Murthy, Brian Doyle, Jack Kavalieros, Robert Chau
  • Publication number: 20030219939
    Abstract: The invention relates to a process of forming a bipolar junction transistor (BJT) that includes forming a topology over a substrate. Thereafter, a spacer is formed at the topology. A base layer is formed from epitaxial silicon above the spacer and at the topology. A leakage block structure is formed in the substrate by out-diffusion from the spacer. Thereafter a BJT is completed with the base layer and the spacer.
    Type: Application
    Filed: April 17, 2003
    Publication date: November 27, 2003
    Inventors: Shahriar Ahmed, Mark Bohr, Stephen Chambers, Richard Green, Anand Murthy
  • Patent number: 6653700
    Abstract: A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: November 25, 2003
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Jack Kavalieros, Anand Murthy, Brian Roberds, Brian S. Doyle
  • Publication number: 20030207127
    Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.
    Type: Application
    Filed: May 30, 2003
    Publication date: November 6, 2003
    Inventors: Anand Murthy, Ravindra Soman, Boyan Boyanov
  • Patent number: 6621131
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: September 16, 2003
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry