Patents by Inventor Anand Murthy

Anand Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF FORMING LOW INTERFACE RESISTANCE CONTACTS AND STRUCTURES FORMED THEREBY
    Publication number: 20120068180
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 22, 2012
    Inventors: Rishabh Mehandru, Bernhard Sell, Anand Murthy, Lucian Shifren
  • GRADED HIGH GERMANIUM COMPOUND FILMS FOR STRAINED SEMICONDUCTOR DEVICES
    Publication number: 20120032265
    Abstract: Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: February 4, 2011
    Publication date: February 9, 2012
    Inventors: Danielle Simonelli, Anand Murthy
  • MULTI-COMPONENT STRAIN-INDUCING SEMICONDUCTOR REGIONS
    Publication number: 20110215375
    Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 8, 2011
    Inventors: Ted E. Cook, JR., Bernhard Sell, Anand Murthy
  • TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER
    Publication number: 20110186912
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Application
    Filed: April 7, 2011
    Publication date: August 4, 2011
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • Transistor gate electrode having conductor material layer
    Patent number: 7968957
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • Multi-component strain-inducing semiconductor regions
    Patent number: 7943469
    Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: May 17, 2011
    Assignee: Intel Corporation
    Inventors: Ted E. Cook, Jr., Bernhard Sell, Anand Murthy
  • Method for improving transistor performance through reducing the salicide interface resistance
    Publication number: 20110101418
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: December 29, 2009
    Publication date: May 5, 2011
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann
  • STRAINED NMOS TRANSISTOR FEATURING DEEP CARBON DOPED REGIONS AND RAISED DONOR DOPED SOURCE AND DRAIN
    Publication number: 20110068403
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 24, 2011
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • Graded high germanium compound films for strained semiconductor devices
    Patent number: 7902009
    Abstract: Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventors: Danielle Simonelli, Anand Murthy
  • TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER
    Publication number: 20110018031
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Application
    Filed: September 29, 2010
    Publication date: January 27, 2011
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • Transistor gate electrode having conductor material layer
    Patent number: 7871916
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: January 18, 2011
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • Method for improving transistor performance through reducing the salicide interface resistance
    Publication number: 20110006344
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: December 29, 2009
    Publication date: January 13, 2011
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann
  • Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
    Patent number: 7858981
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • CMOS transistor junction regions formed by a CVD etching and deposition sequence
    Patent number: 7812394
    Abstract: This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: October 12, 2010
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Glenn A. Glass, Andrew N. Westmeyer, Michael L. Hattendorf, Jeffrey R. Wank
  • Graded high germanium compound films for strained semiconductor devices
    Publication number: 20100148217
    Abstract: Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 17, 2010
    Inventors: Danielle Simonelli, Anand Murthy
  • Semiconductor device having self-aligned epitaxial source and drain extensions
    Patent number: 7732285
    Abstract: A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: June 8, 2010
    Assignee: Intel Corporation
    Inventors: Bernhard Sell, Tahir Ghani, Anand Murthy, Harry Gomez
  • Methods of forming low interface resistance contacts and structures formed thereby
    Publication number: 20100109046
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 6, 2010
    Inventors: Rishabh Mehandru, Bernhard Sell, Anand Murthy, Lucian Shifren
  • Semiconductor transistor having a stressed channel
    Publication number: 20100102356
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Application
    Filed: December 29, 2009
    Publication date: April 29, 2010
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Semiconductor transistor having a stressed channel
    Publication number: 20100102401
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Application
    Filed: December 29, 2009
    Publication date: April 29, 2010
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Formation of strain-inducing films
    Patent number: 7678631
    Abstract: A method to form a strain-inducing three-component epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch step sequence, followed by an amorphizing dopant impurity-implant and, finally, a kinetically-driven crystallization process. In one embodiment, the charge-neutral lattice-substitution atoms are smaller and present in greater concentration than the charge-carrier dopant impurity atoms.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: March 16, 2010
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Glenn Glass, Michael L. Hattendorf