Patents by Inventor Anand Murthy

Anand Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9202889
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A Glass, Thomas Hoffman
  • NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS
    Publication number: 20150221744
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Application
    Filed: April 16, 2015
    Publication date: August 6, 2015
    Applicant: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Enhanced dislocation stress transistor
    Patent number: 9076814
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Nanowire transistor with underlayer etch stops
    Patent number: 9064944
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • ENHANCED DISLOCATION STRESS TRANSISTOR
    Publication number: 20150155384
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 4, 2015
    Applicant: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • ENHANCED DISLOCATION STRESS TRANSISTOR
    Publication number: 20140284626
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: June 6, 2014
    Publication date: September 25, 2014
    Inventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS
    Publication number: 20140264280
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Enhanced dislocation stress transistor
    Patent number: 8779477
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Strained transistor integration for CMOS
    Patent number: 8748869
    Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Anand Murthy, Brian S. Doyle, Robert Chau
  • METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE
    Publication number: 20130302961
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: June 28, 2013
    Publication date: November 14, 2013
    Inventors: Anand Murthy, Boyan Boyanov, Glen A. Glass, Thomas Hoffman
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 8482043
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: July 9, 2013
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A Glass, Thomas Hoffman
  • STRAINED TRANSISTOR INTEGRATION FOR CMOS
    Publication number: 20130153965
    Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
    Type: Application
    Filed: February 11, 2013
    Publication date: June 20, 2013
    Inventors: Boyan Boyanov, Anand Murthy, Brian S. Doyle, Robert Chau
  • Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
    Patent number: 8426858
    Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: April 23, 2013
    Assignee: Intel Corporation
    Inventors: Michael L. Hattendorf, Jack Hwang, Anand Murthy, Andrew N. Westmeyer
  • Strained transistor integration for CMOS
    Patent number: 8373154
    Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Boyan Boyanov, Anand Murthy, Brian S. Doyle, Robert Chau
  • Transistor gate electrode having conductor material layer
    Patent number: 8237234
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: August 7, 2012
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau
  • Multi-component strain-inducing semiconductor regions
    Patent number: 8154087
    Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: April 10, 2012
    Assignee: Intel Corporation
    Inventors: Ted E. Cook, Jr., Bernhard Sell, Anand Murthy
  • METHODS OF FORMING LOW INTERFACE RESISTANCE CONTACTS AND STRUCTURES FORMED THEREBY
    Publication number: 20120068180
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a tapered contact opening in an ILD disposed on a substrate, wherein a source/drain contact area is exposed, preamorphizing a portion of a source drain region of the substrate, implanting boron into the source/drain region through the tapered contact opening, forming a metal layer on the source/drain contact area, and then annealing the metal layer to form a metal silicide.
    Type: Application
    Filed: November 9, 2011
    Publication date: March 22, 2012
    Inventors: Rishabh Mehandru, Bernhard Sell, Anand Murthy, Lucian Shifren
  • GRADED HIGH GERMANIUM COMPOUND FILMS FOR STRAINED SEMICONDUCTOR DEVICES
    Publication number: 20120032265
    Abstract: Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: February 4, 2011
    Publication date: February 9, 2012
    Inventors: Danielle Simonelli, Anand Murthy
  • MULTI-COMPONENT STRAIN-INDUCING SEMICONDUCTOR REGIONS
    Publication number: 20110215375
    Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 8, 2011
    Inventors: Ted E. Cook, JR., Bernhard Sell, Anand Murthy
  • TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER
    Publication number: 20110186912
    Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
    Type: Application
    Filed: April 7, 2011
    Publication date: August 4, 2011
    Inventors: Anand Murthy, Boyan Boyanov, Suman Datta, Brian S. Doyle, Been-Yih Jin, Shaofeng Yu, Robert Chau