Patents by Inventor Anand Murthy

Anand Murthy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ARSENIC-DOPED EPITAXIAL SOURCE/DRAIN REGIONS FOR NMOS
    Publication number: 20200105754
    Abstract: Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm3 to about 5E21 atoms per cm3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon).
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Anand Murthy, Ryan Keech, Nicholas G. Minutillo, Ritesh Jhaveri
  • TRANSISTOR STRUCTURE WITH INDIUM PHOSPHIDE CHANNEL
    Publication number: 20200098757
    Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Applicant: INTEL CORPORATION
    Inventors: Willy Rachmady, Matthew Metz, Gilbert Dewey, Nicholas Minutillo, Cheng-Ying Huang, Jack Kavalieros, Anand Murthy, Tahir Ghani
  • GERMANIUM-RICH NANOWIRE TRANSISTOR WITH RELAXED BUFFER LAYER
    Publication number: 20200091287
    Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Applicant: INTEL CORPORATION
    Inventors: Glenn Glass, Anand Murthy, Cory Bomberger, Tahir Ghani, Jack Kavalieros, Siddharth Chouksey, Seung Hoon Sung, Biswajeet Guha, Ashish Agrawal
  • Methods of forming doped source/drain contacts and structures formed thereby
    Patent number: 10573750
    Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Glenn Glass, Karthik Jambunathan, Anand Murthy, Chandra Mohapatra, Seiyon Kim
  • Methods of forming dislocation enhanced strain in NMOS structures
    Patent number: 10396201
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
  • SYSTEMS, METHODS AND DEVICES FOR ISOLATION FOR SUBFIN LEAKAGE
    Publication number: 20190189749
    Abstract: A subfin leakage problem with respect to the silicon-germanium (SiGe)/shallow trench isolation (STI) interface can be mitigated with a halo implant. A halo implant is used to form a highly resistive layer. For example, a silicon substrate layer 204 is coupled to a SiGe layer, which is coupled to a germanium (Ge) layer. A gate is disposed on the Ge layer. An implant is implanted in the Ge layer that causes the layer to become more resistive. However, an area does not receive the implant due to being protected (or covered) by the gate. The area remains less resistive than the remainder of the Ge layer. In some embodiments, the resistive area of a Ge layer can be etched and/or an undercuttage (etch undercut or EUC) can be performed to expose the unimplanted Ge area of the Ge layer.
    Type: Application
    Filed: September 28, 2016
    Publication date: June 20, 2019
    Applicant: INTEL CORPORATION
    Inventors: Benjamin Chu-Kung, Van Le, Seung Hoon Sung, Jack Kavalieros, Ashish Agrawal, Harold Kennel, Siddharth Chouksey, Anand Murthy, Tahir Ghani, Glenn Glass, Cheng-Ying Huang
  • METHODS OF FORMING SELF ALIGNED SPACERS FOR NANOWIRE DEVICE STRUCTURES
    Publication number: 20180358436
    Abstract: Methods of forming self-aligned nanowire spacer structures are described. An embodiment includes forming a channel structure comprising a first nanowire and a second nanowire. Source/drain structures are formed adjacent the channel structure, wherein a liner material is disposed on at least a portion of the sidewalls of the source/drain structures. A nanowire spacer structure is formed between the first and second nanowires, wherein the nanowire spacer comprises an oxidized portion of the liner.
    Type: Application
    Filed: December 24, 2015
    Publication date: December 13, 2018
    Applicant: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn Glass, Anand Murthy, Jun Sung Kang, Seiyon Kim
  • METHODS OF FORMING DOPED SOURCE/DRAIN CONTACTS AND STRUCTURES FORMED THEREBY
    Publication number: 20180261696
    Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.
    Type: Application
    Filed: December 24, 2015
    Publication date: September 13, 2018
    Inventors: Glenn Glass, Karthik Jambunathan, Anand Murthy, Chandra Mohapatra, Seiyon Kim
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9876113
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 23, 2018
    Assignee: INTEL CORPORATION
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann
  • Semiconductor transistor having a stressed channel
    Patent number: 9735270
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9680016
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 13, 2017
    Assignee: INTEL CORPORATION
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann
  • Enhanced dislocation stress transistor
    Patent number: 9660078
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Nanowire transistor with underlayer etch stops
    Patent number: 9614060
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE
    Publication number: 20160336446
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffman
  • Semiconductor transistor having a stressed channel
    Patent number: 9490364
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani, Kaizad R. Mistry
  • NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS
    Publication number: 20160284821
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Applicant: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • Method for improving transistor performance through reducing the salicide interface resistance
    Patent number: 9437710
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A. Glass, Thomas Hoffman
  • Nanowire transistor with underlayer etch stops
    Patent number: 9385221
    Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Daniel Aubertine, Kelin Kuhn, Anand Murthy
  • ENHANCED DISLOCATION STRESS TRANSISTOR
    Publication number: 20160079423
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Applicant: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
  • Enhanced dislocation stress transistor
    Patent number: 9231076
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine