APPARATUSES, METHODS, AND SYSTEMS FOR NEURAL NETWORKS
Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.
This application is a continuation application of U.S. patent application Ser. No. 16/317,497 filed Jan. 11, 2019, which is a national stage application of International Application No. PCT/US2016/053980 filed Sep. 27, 2016, which claims the benefit of India Provisional Patent Application No. 201641027751 filed Aug. 13, 2016 and entitled “Scalable Processor Architecture for Neural Networks,” which are incorporated herein by reference.
TECHNICAL FIELDThe disclosure relates generally to electronics, and, more specifically, an embodiment of the disclosure relates to a processor to process a neural network.
BACKGROUNDA processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction herein may refer to a macro-instruction, e.g., an instruction that is provided to the processor for execution, or to a micro-instruction, e.g., an instruction that results from a processor's decoder decoding macro-instructions.
The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
In the following description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
A (e.g., hardware) processor, or set of processors, executes instructions from an instruction set, e.g., the instruction set architecture (ISA). The instruction set is the part of the computer architecture related to programming, and generally includes the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term instruction herein may refer to a macro-instruction, e.g., an instruction that is provided to the processor for execution, or to a micro-instruction, e.g., an instruction that results from a processor's decode unit (decoder) decoding macro-instructions. A processor (e.g., having one or more cores to decode and/or execute instructions) may operate on data, for example, in performing arithmetic, logic, or other functions. A processor (e.g., processing system) may process a neural network. In certain embodiments, a (e.g., artificial) neural network generally refers to a group of artificial neurons (e.g., algorithms) that are used to estimate or approximate functions that depend on a large number of inputs that are generally unknown.
Deep Neural Networks (DNNs), a class of machine learning algorithms inspired by the human brain, demonstrate state-of-the-art performance on a variety of recognition tasks and may be ubiquitously employed in many real world applications. However, DNNs may impose significant computational challenges owing to the complexity of the networks and the amount of data they process, both of which may grow in future. To improve the efficiency of both training and evaluating neural networks (e.g., DNNs), certain embodiments herein provide for a dense, scalable compute node architecture, whose compute, memory, and/or interconnect subsystems are specialized to leverage the compute and communication characteristics of DNNs. In certain embodiments herein, the architectural features increase the processing efficiency. Certain embodiments herein include: (i) heterogeneous processing tiles and chips that meet the varying needs of the operations constituting a neural network (e.g., DNN), (ii) a 3-tiered chip/node-level interconnect topology that matches the data-flow present in neural networks (e.g., DNNs), (iii) methods to map neural networks (e.g., DNNs) to a processor (e.g., processing system) that localizes computations to minimize data movement and improves core utilization through nested pipelining, and/or (iv) a low overhead synchronization mechanism based on hardware dataflow trackers. In one embodiment herein, a processor (e.g., processing system) to process a neural network may deliver 680 TFLOPs peak at 1.4 KW of power consumption, e.g., to achieve 6 to 28 times improvement in performance on a DNN topologies containing 0.65-14.9 million neurons and 6.8-145.9 million weights, for example, a processor with 7032 cores operating at 600 MHz.
A processor (e.g., processing system) to process a neural network may be a computing system made up of a number of (e.g., highly) interconnected processing elements, which process information by their dynamic state response to external inputs. With an increase in the amount of digital data and the proliferation of connected devices, DNNs may receive significant interest, and represent the state-of-the-art on a variety of video, image, audio, and text recognition problems. DNNs may be widely deployed in many real-world applications, for example, an internet image search, voice activated software (e.g., search or language translation), among many more, for example, in the fields of autonomous vehicles, biomedicine, virtual reality etc. While neural networks (e.g., DNNs) enable significant applications, training and/or evaluating neural networks (e.g., DNNs) may be highly compute and data intensive. Two example scenario of an extreme computational challenge imposed by neural networks (e.g., DNNs) are: (i) an embedded inference, in which neural networks (e.g., DNNs) are deployed and evaluated on energy-constrained devices (such as Internet-of-Things (IoT) edge devices) and (ii) cloud-based training, in which neural networks (e.g., DNNs) are trained on the cloud under stringent performance constraints.
Certain neural networks utilize one or a plurality of giga-floating point operations per second (GFLOPs) or petaFLOPs (PFLOPs), e.g., for evaluating a single input. For example, a neural network for image recognition may contain about 820 K neurons and about 145 M parameters, and utilize around 3.3 giga-floating point operations per second (GFLOPs) for evaluating a single 230×230 input image. Similarly, training for one epoch (e.g., the presentation of the entire training set to the neural network) on a dataset with 1.2 million images may consume about 15 petaFLOPs (PFLOPs) of processing resources. Certain embodiments of learning algorithms, such as Stochastic Gradient Descent (SGD), may take 50-100 epochs to converge, e.g., making neural network training an exascale problem. The processing resources for training and evaluating neural networks (e.g., DNNs) may rapidly increase (e.g., greater than 10×), as larger datasets and networks of higher complexity (e.g., more layers, more features, larger feature sizes, etc.) are actively explored and developed.
Certain embodiments herein include a compiler front-end to program a (e.g., any) neural network (e.g., DNN) topology to a processor (e.g., a processing system), and/or a detailed cycle-accurate architectural simulator to estimate performance and energy. The simulator may also incorporate power models based on gate-level synthesis to a processor's (e.g., 14 nm) technology node. Although certain embodiments herein refer to use with a Deep Neural Network (DNN), other neural networks may be utilized.
The following sections discuss embodiments of computational characteristics of neural networks (e.g., DNNs) in Section I, embodiments of computing architecture in Section II, embodiments of a compiler front-end for programming in Section III, examples of an evaluation methodology in Section IV, and example results of the evaluation methodology in Section V.
I. Computational CharacteristicsThe below section describes example algorithms to train and evaluate Deep Neural Networks (DNNs), and identify the (e.g., key) computation patterns involved in their realization. This section then presents a detailed analysis of an example DNN workload and uses it to quantify the computational challenges in implementing those DNNs and highlight the opportunities to improve their efficiency.
A. PreliminariesIn certain embodiments, the fundamental compute primitive of a neural network (e.g., DNN) is an artificial neuron. Each neuron may be associated with a set of parameters called weights. In one embodiment, the neuron is a multiple-input and one-output function, e.g., which evaluates weighted sum of its inputs followed by an (e.g., non-linear) activation function to produce the output. DNNs may be comprised of several (e.g., millions of) neurons connected to each other. While any variant of neural networks (e.g., DNNs) may be utilized, the below is generally related to feedforward networks in which the network is organized in layers, e.g., with neurons in a given layer connected only to neurons in the successive layer. In one embodiment, DNNs are operated in two phases: (i) Training/Learning and (ii) Testing/Evaluation. In the training phase, a training dataset labeled with (e.g., golden) class outputs may be used to learn the network parameters. In the testing phase, the trained network may be deployed and used to classify a given input into one of the output classes. Additionally or alternatively to improving the evaluation phase, certain embodiments of a processor (e.g., processing system) architecture improve the efficiency of both the training and testing phases. The training process may encompass the steps carried out during network evaluation, and therefore describe DNN training in more detail.
B. Neural Network Training: Data FlowTurning to the Figures,
The network-level data flow in each iteration of this DNN training is shown in
-
- Forward Propagation (FP): Neurons in each layer are evaluated in succession until the network outputs are reached. Computations corresponding to each layer may start (e.g., only) after the previous layer is complete, whereas neurons within each layer may be evaluated in parallel.
- Backpropagation (BP): The difference between the golden and network outputs is evaluated. The error at the output is propagated back through the network. The computations are similar to FP, e.g., error at an input of a layer is computed as the weighted sum of the errors at the output of each neuron fed by the input. Errors may be backpropagated through all neurons in a layer in parallel, while BP for a layer may commence (e.g., only) after BP through its successive layer is complete.
- Weight Gradient and Update (WG): The amount by which each weight in the network is modulated is generally referred to as the weight gradient. It may be computed by accumulating the product of the FP outputs and BP errors corresponding to a given weight. Thus gradients corresponding to each weight in a layer may be computed in parallel, e.g., as soon as the error at the output of the layer is available. In certain embodiments, training iterations are repeated several times over the entire training dataset (e.g., referred to as epochs) until the weights converge. In one embodiment, multiple training inputs are grouped into a minibatch. The FP, BP, and WG steps corresponding to each input in a minibatch may be computed in parallel. After this, their gradients may be accumulated together to update the network weights. Algorithmically, as gradients are averaged, minibatching may smoothen convergence, e.g., while yielding significant parallelism from a compute perspective. In one embodiment, DNN evaluation involves (e.g., only) the FP step, and the test inputs are labelled the class corresponding to the neuron with the largest value at the network outputs. The computations performed during the FP, BP and WG steps may vary based on the layer type, e.g., which broadly defines how neurons of a layer are connected to the layer inputs. In certain embodiments, there are three types of layers, and
FIGS. 2-4 illustrates the layer-level data flow for each layer type, respectively.
Convolutional (CONV) Layer: The neurons in a convolutional layer may be arranged as multiple dimensional grids (e.g., two, three, four dimensional, etc.) called features. In one embodiment, the layer takes multiple input features and produces multiple feature outputs. In the case of FP, each output feature may be computed by: (i) convolving each input feature with a weight matrix called a kernel, (ii) accumulating the convolved output features, and (iii) performing an (e.g., non-linear) activation function on the accumulated sum. This process may be repeated for all output features. In some cases, a connection table denoting which input and output features are connected is specified. The BP/WG steps may be formulated similarly as convolutions followed by accumulations.
Sampling (SAMP) Layer: These layers may take multiple input features and produce a (e.g., equal) plurality of output features. In FP, output features may be produced by down-sampling (e.g., max-pooling or averaging) the input features, e.g., reducing feature size. Similarly, errors may be up-sampled during BP. In certain embodiment, these layers do not contain weights and hence no WG is performed.
Fully-Connected (FC) Layer: Neurons of a fully connected layer may be organized as a vector. In certain embodiments, each neuron is connected to all layer inputs through a distinct weight. The FP/BP steps may be formulated as a vector-matrix multiplication followed by activation function. The WG step may be an element-wise product of the FP output and BP error vectors. A deep network may include a series of convolution layers (e.g., 5-30 CONV layers) followed by (e.g., fewer) fully connected layers (e.g., 1-3 FC layers). Sampling layers may follow some convolutional layers. The convolutional layers may extract local features by moving the kernel across the input features. As processing progress through the neural network (e.g., DNN), local features may be composed to construct global features, e.g., which are then used by the fully connected layers to classify the input.
C. Workload AnalysisInter-layer Heterogeneity: To demonstrate the heterogeneity across layers,
Intra-layer Heterogeneity: In this example neural network, computations that constitute a layer also exhibit differing computational characteristics. In the initial convolutional layers in this example neural network, convolution accounts for about 98% of the FLOPs, while feature accumulation and activation function contribute the rest. The mid convolutional layers in this example neural network are still dominated by convolution (about 94%), but as feature counts grow, feature accumulation carries a larger fraction of FLOPs. In fully connected layers in this example neural network, almost all FLOPs may result from vector-matrix multiplication.
Certain embodiments herein provide for a dense, scalable compute node architecture, for example, built from the ground-up for deep networks. Certain embodiments herein provide specialized compute cores, memory hierarchy, and/or interconnect topologies, e.g., to leverage the key compute and the data flow patterns of deep networks. This section describes architectural features, for example, from which certain embodiments herein derive their efficiency.
A. Heterogeneous Processing TilesCertain embodiments herein (e.g., of a processor) aggressively exploit the heterogeneity in the computations within and across layers of a neural network.
-
- (1) Compute Intensive Tile:
Array Reconfigurability. The architectural (e.g., design) parameters of a compute intensive tile may be the number of rows, columns, and lanes in the multiple dimensional (e.g., 2D) processing array, and/or the sizes of the left, top, bottom, and/or auxiliary memories. In certain embodiments, e.g., to improve utilization of compute intensive tile(s), some architectural parameters may be configured at runtime, e.g., through a circuit or software instructions. In one embodiment, the following parameters are adjustable: the columns and lanes of the 2D-PE array may be redistributed (for example, while maintaining their product constant, e.g., to dynamically increase or decrease) the number of columns in the array by proportionately reducing (or increasing) the number of lanes per 2D-PE. This configurability may be useful as feature counts and kernel sizes vary across convolutional layers, e.g., and fully connected layers involve a single matrix multiplication (e.g., the lanes to 2D-PE ration is set to 1). The 2D-PE array may be split along the rows into two 2D arrays with half the number of rows. The streaming memory elements on the left may also be split in half, e.g., while the top and bottom streaming memory elements individually feed the columns of the 2D arrays. This may allow for two batch operations (e.g., convolutions or matrix multiplications) to be executed in parallel. This configurability may be desirable to reduce the number of residual rows when the feature sizes of the convolutional layers are small, e.g., do not utilize all or most of the rows.
-
- (2) Memory Intensive Tile:
Certain chip architectures disclosed herein combine compute intensive and memory intensive tiles (e.g., on a single chip) in a manner that leverages the data flow patterns in neural networks (e.g., DNNs). The following subsections describe embodiments of the architecture in more detail.
-
- (1) Architecture Description:
-
- (2) Execution Model and Instruction Set Architecture (ISA):
-
- Scalar Control Instructions 1002: e.g., load/store, scalar operations and branch instructions primarily used to determine program control flow. They may be executed on the scalar processing element (PE) of a compute intensive tile.
- Coarse-grained Data Instructions 1004: e.g., compute dominant instructions such as convolutions (nD-convolutions), etc. They may be executed on the PE arrays of a compute intensive tile.
- Memory Intensive Tile Offload Instructions 1006: e.g., high Bytes/FLOP instructions such as down-sampling (NDSUBSAMP) etc. They may be offloaded for execution to one of the memory intensive tiles connected to a compute intensive tile.
- Memory Intensive Tile Data Transfer Instructions 1008: e.g., where the memory hierarchy is already (e.g., hardware or software) managed, these instructions may initiate data transfer between connected memory intensive tiles.
- Data-flow Track Instructions 1010: e.g., instructions used to track accesses to specified data structures (e.g., address ranges). These may be used to enforce synchronized execution, for example, as explained in Section II-B4 For certain embodiments that specifically target deep networks, e.g., those whose computations and data flow are static without any (e.g., complex) data-dependent control flows, those certain embodiments may be programmed with minimal programmer burden. To this end, a circuit and/or compiler front-end may automatically map any neural (e.g., deep) network topology to a processor (e.g., processing system), for example, the processor discussed in Section II.
- (3) Implementing DNN Layers on a Processor (e.g., Chip):
This disclosure now describes how DNNs are realized on an embodiment of chip architecture. Layers of the DNN may be spatially realized across the entire chip, e.g., by allocating a set of columns to each layer based on its compute and memory requirements.
Distributed Network State and Localized Computations: One key aspect of the mapping process is that (e.g., at compile time), the entire network state (e.g., features, errors, weights, and weight gradients) is partitioned and distributed across the memory intensive tiles in the chip. In one embodiment, each feature and error in the network is assigned a home memory intensive tile. Enough memory capacity may be provisioned, e.g., cumulatively across all memory intensive tiles, to hold all the features and errors of the network. In one embodiment, a neural (e.g., deep) network includes a few million neurons and utilizes 10s' of MB of memory capacity, e.g., which may be provisioned on-chip. In an embodiment when the features and errors do not fit on a single chip, the neural network may be split at the node-level and multiple chips utilized to realize the neural network. An embodiment of this is discussed in the context of the node architecture described in Section II-C. In one embodiment, e.g., depending on the memory capacity available, weights and weight gradients of selected layers are stored on-chip, e.g., in the memory intensive tiles where the corresponding features reside. Weights and gradients of the other layers may be stored in external memory, for example, and are prefetched into the memory intensive tiles (e.g., the (FIFO queue) of a memory intensive tile). The compute intensive tiles may produce and consume the neural network state stored in memory intensive tiles, e.g., those tiles directly connected to them. The SFUs present within the memory intensive tiles may also operate on the neural network state stored in them. In one embodiment, by partitioning the network state and associated computations spatially across multiple processing tiles of a chip, data movement is localized and/or interconnect bandwidth is minimized. This, e.g., coupled with a simplified memory hierarchy, may significantly add to the energy efficiency of a processor (e.g., chip).
Illustration: Convolutional Layer Forward Propagation (FP): FIG. 11illustrates the computations realized on a chip 1100 with compute intensive tiles and memory intensive tiles for the forward propagation of a convolutional layer according to embodiments of the disclosure.
Realizing Layer Sequences: Successive layers of a neural network (e.g., DNN) may be mapped to adjacent sets of columns in the chip. In certain embodiments, this leverages the producer and consumer relationship between layers of a neural network (e.g., DNN). In the case of FP, inputs to the DNN may be fetched from external memory by the columns that realize the first layer. From then, outputs of a layer produced by a set of columns may be consumed by the next, e.g., until the FP outputs are obtained. The final set of FP tiles may also compute the error at network outputs, e.g., by finding the difference between the golden and FP outputs. BP and WG may be realized in a similar fashion, for example, with use of their respective compute intensive tile and the direction of data flow is reversed. The weight gradients may be either stored to the external memory or on-chip. The errors may be discarded after BP/WG of the layer is complete.
Nested Pipelining:
-
- (4) Synchronization Using Data Flow Trackers:
In certain embodiments, e.g., to achieve correct functionality, the programs executing on the different compute intensive tiles are to be synchronized. In certain embodiments, a full-fledged coherence protocol and/or a lock-based synchronization scheme is utilized. In certain embodiments, a full-fledged coherence protocol and/or a lock-based synchronization scheme is not used, e.g., where it imposes significant energy overheads. Certain embodiments herein leverage two key properties: (i) the data access sequence to each location in memory may be ascertained before execution (e.g., at compile time) where both the data flow in neural (e.g., deep) network and the schemes adopted to partition computations are static, and (ii) accumulation is commutative, e.g., when updates from multiple sources are accumulated at a given memory location, the end result is not affected by the order in which the updates are received. To this end, the following synchronization operation (e.g., instruction) may be used:
MEMTRACK (AddRange, NumUpdates, NumReads)
which when (e.g., decoded and) executed, specifies an address range (AddRange) operand, an operand of the number of updates the address range should receive before it is to be read (NumUpdates), and number of reads to the address range before it is to be written (NumReads) operand. In one embodiment, the compute intensive tile offloads the MEMTRACK instruction to the appropriate memory intensive tile, for example, which then utilizes hardware counters to track accesses to the address range, e.g., to ensure the access sequence conforms to the specifications. R may refer to a register operand. In certain embodiments, the MEMTRACK operation causes hardware to deny reads and writes that violate the access sequence. Disallowing read and write transactions may be achieved by: (i) delaying the transaction by inserting it at the end of the memory queue, and retrying once it progresses to the head, or (ii) sending a deny (e.g., NACK) signal to the processing element, e.g., so that it retries the transaction at a later time. A memory intensive tile may queue up requests that arrive out of the specified order or NACK them, e.g., if the queue is full. Thus certain embodiments herein enforce synchronized execution with (e.g., very) low overhead.
-
- (5) Heterogeneous Chip Designs:
Certain embodiments use one or more components of the architectural template described above in two different chips, for example, a convolutional layer (e.g., ConvLayer) chip and fully connected layer (e.g., FCLayer) chip.
Certain embodiments herein use the heterogeneity between multiple layers of a neural network (e.g., the convolutional and fully connected layers of a DNN, e.g., as discussed above in reference to
-
- The fully connected layer chip may have fewer compute FLOPs. The compute intensive tiles have fewer 2D-PEs. For example, to cater to matrix multiplication as opposed to batch convolutions, the 2D array may have fewer rows, more columns, and each 2D-PE has only a single lane. Further, the fully connected layer chip may contains fewer columns, e.g., for a DNNs that has fewer fully connected layers than convolutional layers.
- The memory arrays of the fully connected layer chip may be organized differently. For example, in a fully connected layer chip, the compute intensive tiles may have smaller auxiliary memory space and/or larger left, top, and bottom memory elements (e.g., streaming memory elements). The data array in the memory intensive tiles may be larger and/or be fewer in number owing to fewer chip columns.
- The on-chip and off-chip links in the fully connected layer chip may be designed to support higher bandwidth, e.g., when fully connected layers possess a larger number of weights. Embodiments of the micro-architectural parameters of the chips and their on/off-chip bandwidth are discussed in Section IV.
In certain embodiments, at the node level, multiple convolutional layer and fully connected layer chips are interconnected in a two-tiered hierarchy to form a compute node. This subsection described the interconnectivity at the node-level.
-
- (1) Chip Cluster—Wheel of Convolutional Layer and Fully Connected Layer Chips:
In certain embodiments, one of the key performance parameters at the node-level is for the substantially high memory bandwidth required by the fully connected layer chips to maintain a same throughput as the convolutional layer chips. One embodiment herein reduces the memory bandwidth by aggregating inputs to the fully connected layers, e.g., and execute them as a batch in the fully connected layer chip. This may allow for the layer parameters to be fetched only once per batch, e.g., reducing bandwidth proportional to the batch size.
-
- (2) Ring of Chip Clusters:
Multiple chip clusters may be coupled (e.g., connected) as a ring, e.g., ring 1504 in
To program a processor (e.g., a processing system), for example, the processor in
In one embodiment, the workload mapping phase allocates chip columns for each layer in the neural network (e.g., DNN) and determines how the network state and computations are to be distributed across the memory intensive and compute intensive tiles of the allocated columns.
In certain embodiments, the code generation phase produces programs for each compute intensive tile in the processor (e.g., processing system). One embodiment of a circuit and/or compiler comprises a library of assembly templates for the FP/BP/WG steps of each layer type. These parameterized assembly templates may be customized based on the information (e.g., features per memory intensive tile) available, e.g., from the workload mapping phase. As an example, a code snippet 1802 compiled to the ISA in
In this section, the methodology used to evaluate certain embodiments herein is described.
Performance Evaluation: certain embodiments herein are evaluated on a detailed and cycle-accurate architectural simulator. The simulator may rigorously model (e.g., all) events that occur in each execution cycle, including every compute operation, on/offchip memory access, and data transfer.
Power and Energy Estimation: To estimate compute power, compute intensive and memory intensive tile execution arrays may be synthesized to semiconductor (e.g., 14 nm) technology node and the power measured at gate-level. The power consumed by the different components may be incorporated into the simulator, and energy estimated based on the dynamic execution traces observed during simulation.
Architectural Configuration:
Benchmarks. To evaluate one embodiment of a processor, eleven image recognition DNN topologies, as noted below in Table 1, are used as the benchmarks. The benchmark networks contain between 11-39 layers (5-33 convolutional, 1-3 fully connected, 3-5 SAMP), 0.65-14.9 million neurons, and 6.8-145.9 million weights.
In this section, we present the results that demonstrate the benefits of certain embodiments herein.
A. Training and Evaluation PerformancePerformance Comparison. Certain embodiments herein produce a 7×-28× increase in performance with respect to a GPU implementation.
Layer-wise Performance Analysis.
The average power consumed by the different benchmarks during training of the DNN embodiments in
The below discusses the utilization of the on-chip, chip cluster-level, and node-level links for each benchmark during training of the DNN embodiments in
The advent of (e.g., deep) neural networks across the spectrum of computing devices, from mobile to cloud, allows for implementation efficiency with certain embodiments herein, for example, a specialized node architecture for training and evaluating DNNs. The architecture may include heterogeneous processing tiles, for example, compute intensive tile and memory intensive tiles, and compute chips for example, convolutional layer chip and fully connected layer chip, e.g., interconnected using a 3-tiered grid-wheel-ring topology. Embodiments herein leverage the computation and communication patterns prevalent in DNNs. Certain embodiments herein map a (e.g., any) DNN topology to a processor that distributes network state to localize compute and data movement, e.g., and improves utilization through nested pipelining. Certain embodiments herein provide an order of magnitude improvement in performance and energy efficiency. Certain embodiments herein may be trained for a DNN in less than one or two days.
Certain embodiments herein specialize all the subsystems, including the compute cores, memory hierarchy, and interconnect topology so as to leverage the key computation and data access patterns in DNNs, e.g., leading to drastic improvements in performance and energy efficiency. Certain embodiments herein (for example, a processor (e.g., processing system)) target both training and evaluation of DNNs, e.g., in contrast to exclusively focusing on network evaluation. Certain embodiments herein target a different implementation context than stand-alone accelerator cores. Certain embodiments herein provide a scalable node-level architecture utilizing many (e.g., thousands) of such processing cores, and how best to partition computations amongst them to optimize core utilization, memory bandwidth, and reduce synchronization overheads. Example architectural features from which certain embodiments herein derive their performance/efficiency are: heterogeneous processing tiles and compute chips that aggressively exploit the varying computational characteristics of DNNs both within a layer and across layers, a 3-tiered grid-wheel-ring interconnect topology that matches the communication characteristics of certain DNNs, methods to map DNNs to architecture that localizes computations to minimize data movement, and improves core utilization through nested pipelining, and a low-overhead scheme to enforce synchronized execution using hardware data-flow trackers.
In certain embodiments, one, a plurality (e.g., subset), or all of the above features may be utilized in a processor. In another embodiment, the compute intensive and memory intensive tiles may be replaced with a processing core and a (e.g., Basic Linear Algebra Subprograms (BLAS)) accelerator, respectively, that utilize the interconnect topology and mapping strategy discussed herein.
In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips; and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips includes an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile. Each of the plurality of fully connected layer chips and the plurality of convolutional layer chips may include a plurality of rows and columns of compute intensive tiles coupled to a plurality of rows and columns of memory intensive tiles. Each memory intensive tile may include storage for a multiple dimensional data array and a plurality of functional units coupled to the storage. Each compute intensive tile may include a multiple dimensional array of processing elements. The forward propagation compute intensive tile, the back propagation compute intensive tile, and the weight gradient compute intensive tile may fetch an input feature from the first memory intensive tile and store an output feature into the second memory intensive tile. Partial output features from the compute intensive tiles may be accumulated into a third memory intensive tile to compute an activation function. A convolution layer chip may operate on a set of inputs in parallel to generate updated weight gradients and a respective fully connected layer chip is to operate on a set of outputs from the convolution layer chip. The apparatus to process the neural network may include a circuit to map fully connected layers of the neural network to the plurality of fully connected layer chips and map convolution layers of the neural network to the plurality of convolutional layer chips.
In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by a ring interconnect; a plurality of convolutional layer chips each coupled by a wheel interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips; and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips comprises a multiple dimensional grid interconnect coupling columns of compute intensive tiles to columns of memory intensive tiles, with a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of the compute intensive tiles each coupled between a first memory intensive tile and a second memory intensive tile of the memory intensive tiles.
In another embodiment, a method includes receiving a neural network comprising a plurality of fully connected layers and a plurality of convolutional layers with a processing system, wherein the processing system comprises a plurality of fully connected layer chips coupled by an interconnect, a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips, and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips comprising an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile; and mapping the plurality of fully connected layers of the neural network to the plurality of fully connected layer chips and the plurality of convolution layers of the neural network to the plurality of convolutional layer chips. The method may include generating updated weight gradients for the neural network with the processing system. The method may include a convolution layer chip operating on a set of inputs in parallel to generate updated weight gradients and a respective fully connected layer chip operating on a set of outputs from the convolution layer chip. The method may include accumulating partial output features from the compute intensive tiles into a third memory intensive tile, and computing an activation function. The method may include each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including a plurality of rows and columns of compute intensive tiles coupled to a plurality of rows and columns of memory intensive tiles, and the mapping including allocating columns for each layer of the neural network to the memory intensive tiles. The mapping may include distributing errors of each layer across its allocated columns of the memory intensive tiles. The mapping may include distributing features of each layer across its allocated columns of the memory intensive tiles. The mapping may include assigning computation of a forward propagation function, a back propagation function, and a weight gradient function to a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of the plurality of rows and columns of compute intensive tiles.
In yet another embodiment, a non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method including receiving a neural network comprising a plurality of fully connected layers and a plurality of convolutional layers with a processing system, wherein the processing system comprises a plurality of fully connected layer chips coupled by an interconnect, a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips, and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips comprising an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile; and mapping the plurality of fully connected layers of the neural network to the plurality of fully connected layer chips and the plurality of convolution layers of the neural network to the plurality of convolutional layer chips. The method may include generating updated weight gradients for the neural network with the processing system. The method may include a convolution layer chip operating on a set of inputs in parallel to generate updated weight gradients and a respective fully connected layer chip operating on a set of outputs from the convolution layer chip. The method may include accumulating partial output features from the compute intensive tiles into a third memory intensive tile, and computing an activation function. The method may include each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including a plurality of rows and columns of compute intensive tiles coupled to a plurality of rows and columns of memory intensive tiles, and the mapping including allocating columns for each layer of the neural network to the memory intensive tiles. The mapping may include distributing errors of each layer across its allocated columns of the memory intensive tiles. The mapping may include distributing features of each layer across its allocated columns of the memory intensive tiles. The mapping may include assigning computation of a forward propagation function, a back propagation function, and a weight gradient function to a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of the plurality of rows and columns of compute intensive tiles.
In another embodiment, an apparatus to process a neural network includes a plurality of fully connected layer means coupled by an interconnect; a plurality of convolutional layer means each coupled by an interconnect to a respective fully connected layer means of the plurality of fully connected layer means; and each of the plurality of fully connected layer means and the plurality of convolutional layer means includes an interconnect to couple each of a forward propagation compute intensive means, a back propagation compute intensive means, and a weight gradient compute intensive means of a column of compute intensive means between a first memory intensive means and a second memory intensive means. Each of the plurality of fully connected layer means and the plurality of convolutional layer means may include a plurality of rows and columns of compute intensive means coupled to a plurality of rows and columns of memory intensive means. Each memory intensive means may include storage for a multiple dimensional data array and a plurality of functional units coupled to the storage. Each compute intensive means may include a multiple dimensional array of processing elements. The forward propagation compute intensive means, the back propagation compute intensive means, and the weight gradient compute intensive means may fetch an input feature from the first memory intensive means and store an output feature into the second memory intensive means. Partial output features from the compute intensive means may be accumulated into a third memory intensive means to compute an activation function. A convolution layer means may operate on a set of inputs in parallel to generate updated weight gradients and a respective fully connected layer means is to operate on a set of outputs from the convolution layer means. The apparatus to process the neural network may include a circuit to map fully connected layers of the neural network to the plurality of fully connected layer means and map convolution layers of the neural network to the plurality of convolutional layer means.
In yet another embodiment, an apparatus comprises a data storage device that stores code that when executed by a hardware processor causes the hardware processor to perform any method disclosed herein. An apparatus may be as described in the detailed description. A method may be as described in the detailed description.
In another embodiment, a non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising any method disclosed herein.
An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or subformats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. A set of SIMD extensions referred to as the Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX) coding scheme has been released and/or published (e.g., see Intel® 64 and IA-32 Architectures Software Developer's Manual, June 2016; and see Intel® Architecture Instruction Set Extensions Programming Reference, February 2016).
Exemplary Core Architectures, Processors, and Computer ArchitecturesProcessor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.
Exemplary Core Architectures In-Order and Out-of-Order Core Block DiagramIn
The front end unit 2330 includes a branch prediction unit 2332 coupled to an instruction cache unit 2334, which is coupled to an instruction translation lookaside buffer (TLB) 2336, which is coupled to an instruction fetch unit 2338, which is coupled to a decode unit 2340. The decode unit 2340 (or decoder or decoder unit) may decode instructions (e.g., macro-instructions), and generate as an output one or more micro-operations, micro-code entry points, micro-instructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit 2340 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core 2390 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in decode unit 2340 or otherwise within the front end unit 2330). The decode unit 2340 is coupled to a rename/allocator unit 2352 in the execution engine unit 2350.
The execution engine unit 2350 includes the rename/allocator unit 2352 coupled to a retirement unit 2354 and a set of one or more scheduler unit(s) 2356. The scheduler unit(s) 2356 represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s) 2356 is coupled to the physical register file(s) unit(s) 2358. Each of the physical register file(s) units 2358 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit 2358 comprises a vector registers unit, a write mask registers unit, and a scalar registers unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. The physical register file(s) unit(s) 2358 is overlapped by the retirement unit 2354 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit 2354 and the physical register file(s) unit(s) 2358 are coupled to the execution cluster(s) 2360. The execution cluster(s) 2360 includes a set of one or more execution units 2362 and a set of one or more memory access units 2364. The execution units 2362 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scheduler unit(s) 2356, physical register file(s) unit(s) 2358, and execution cluster(s) 2360 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 2364). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.
The set of memory access units 2364 is coupled to the memory unit 2370, which includes a data TLB unit 2372 coupled to a data cache unit 2374 coupled to a level 2 (L2) cache unit 2376. In one exemplary embodiment, the memory access units 2364 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 2372 in the memory unit 2370. The instruction cache unit 2334 is further coupled to a level 2 (L2) cache unit 2376 in the memory unit 2370. The L2 cache unit 2376 is coupled to one or more other levels of cache and eventually to a main memory.
By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 2300 as follows: 1) the instruction fetch 2338 performs the fetch and length decoding stages 2302 and 2304; 2) the decode unit 2340 performs the decode stage 2306; 3) the rename/allocator unit 2352 performs the allocation stage 2308 and renaming stage 2310; 4) the scheduler unit(s) 2356 performs the schedule stage 2312; 5) the physical register file(s) unit(s) 2358 and the memory unit 2370 perform the register read/memory read stage 2314; the execution cluster 2360 perform the execute stage 2316; 6) the memory unit 2370 and the physical register file(s) unit(s) 2358 perform the write back/memory write stage 2318; 7) various units may be involved in the exception handling stage 2322; and 8) the retirement unit 2354 and the physical register file(s) unit(s) 2358 perform the commit stage 2324.
The core 2390 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.), including the instruction(s) described herein. In one embodiment, the core 2390 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.
It should be understood that the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).
While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture. While the illustrated embodiment of the processor also includes separate instruction and data cache units 2334/2374 and a shared L2 cache unit 2376, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.
Specific Exemplary In-Order Core ArchitectureThe local subset of the L2 cache 2404 is part of a global L2 cache that is divided into separate local subsets, one per processor core. Each processor core has a direct access path to its own local subset of the L2 cache 2404. Data read by a processor core is stored in its L2 cache subset 2404 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 2404 and is flushed from other subsets, if necessary. The ring network ensures coherency for shared data. The ring network is bi-directional to allow agents such as processor cores, L2 caches and other logic blocks to communicate with each other within the chip. Each ring data-path is 1012-bits wide per direction.
Thus, different implementations of the processor 2500 may include: 1) a CPU with the special purpose logic 2508 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores), and the cores 2502A-N being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, a combination of the two); 2) a coprocessor with the cores 2502A-N being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 2502A-N being a large number of general purpose in-order cores. Thus, the processor 2500 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 2500 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.
The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units 2506, and external memory (not shown) coupled to the set of integrated memory controller units 2514. The set of shared cache units 2506 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof. While in one embodiment a ring based interconnect unit 2512 interconnects the integrated graphics logic 2508, the set of shared cache units 2506, and the system agent unit 2510/integrated memory controller unit(s) 2514, alternative embodiments may use any number of well-known techniques for interconnecting such units. In one embodiment, coherency is maintained between one or more cache units 2506 and cores 2502-A-N.
In some embodiments, one or more of the cores 2502A-N are capable of multi-threading. The system agent 2510 includes those components coordinating and operating cores 2502A-N. The system agent unit 2510 may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores 2502A-N and the integrated graphics logic 2508. The display unit is for driving one or more externally connected displays.
The cores 2502A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 2502A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.
Exemplary Computer ArchitecturesReferring now to
The optional nature of additional processors 2615 is denoted in
The memory 2640 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 2620 communicates with the processor(s) 2610, 2615 via a multi-drop bus, such as a frontside bus (FSB), point-to-point interface such as QuickPath Interconnect (QPI), or similar connection 2695.
In one embodiment, the coprocessor 2645 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like. In one embodiment, controller hub 2620 may include an integrated graphics accelerator.
There can be a variety of differences between the physical resources 2610, 2615 in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like.
In one embodiment, the processor 2610 executes instructions that control data processing operations of a general type. Embedded within the instructions may be coprocessor instructions. The processor 2610 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 2645. Accordingly, the processor 2610 issues these coprocessor instructions (or control signals representing coprocessor instructions) on a coprocessor bus or other interconnect, to coprocessor 2645. Coprocessor(s) 2645 accept and execute the received coprocessor instructions.
Referring now to
Processors 2770 and 2780 are shown including integrated memory controller (IMC) units 2772 and 2782, respectively. Processor 2770 also includes as part of its bus controller units point-to-point (P-P) interfaces 2776 and 2778; similarly, second processor 2780 includes P-P interfaces 2786 and 2788. Processors 2770, 2780 may exchange information via a point-to-point (P-P) interface 2750 using P-P interface circuits 2778, 2788. As shown in
Processors 2770, 2780 may each exchange information with a chipset 2790 via individual P-P interfaces 2752, 2754 using point to point interface circuits 2776, 2794, 2786, 2798. Chipset 2790 may optionally exchange information with the coprocessor 2738 via a high-performance interface 2739. In one embodiment, the coprocessor 2738 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.
A shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
Chipset 2790 may be coupled to a first bus 2716 via an interface 2796. In one embodiment, first bus 2716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.
As shown in
Referring now to
Referring now to
Embodiments (e.g., of the mechanisms) disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the disclosure may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
Program code, such as code 2730 illustrated in
The program code may be implemented in a high level procedural or object oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.
Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
Accordingly, embodiments of the disclosure also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.
Emulation (Including Binary Translation, Code Morphing, etc.)In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.
Claims
1. An apparatus comprising:
- a first parallel compute device comprising a plurality of chips, the plurality of chips including a first chip coupled to a first memory device and a second chip coupled to a second memory device;
- a first interconnect to couple the first chip and the second chip; and
- an interface to couple the first parallel compute device to one or more additional parallel compute devices;
- the first chip comprising: a first scalar register file to store data related to control flow operations; first scalar execution circuitry to execute one or more scalar instructions to perform control flow operations in accordance with the data to control execution of an instruction sequence, the control flow operations including program loops, branches, and address calculations, and the instruction sequence including a first matrix multiply instruction; a first decoder to decode the instructions of the instruction sequence including the first matrix multiply instruction, the first matrix multiply instruction to specify multiplication of a first matrix by a second matrix; and a first matrix processing unit comprising a first array of processing elements to perform a plurality of parallel fused multiply-accumulate operations in accordance with the first matrix multiply instruction to multiply first data elements of the first matrix by corresponding second data elements of the second matrix to generate a corresponding plurality of products, and to add the plurality of products to corresponding accumulated values to generate a result matrix.
2. The apparatus of claim 1, wherein the first matrix multiply instruction is to further specify a first size associated with the first matrix and a second size associated with the second matrix.
3. The apparatus of claim 1, wherein the second chip comprises:
- a second scalar register file to store data related to control flow of a first program or a second program;
- second scalar execution circuitry to execute one or more scalar instructions to perform control flow operations related to execution of the second program in accordance with the data, the control flow operations including program loops, branches, and address calculations;
- a second decoder to decode a second matrix multiply instruction, the second matrix multiply instruction to specify multiplication of a third matrix by a fourth matrix, the second matrix multiply instruction to indicate a third matrix size of the third matrix and a fourth matrix size of the fourth matrix; and
- a second matrix processing unit comprising a second array of processing elements to perform a second plurality of parallel fused multiply-accumulate operations in accordance with the second matrix multiply instruction to multiply third data elements of the third matrix by corresponding fourth data elements of the fourth matrix to generate a second corresponding plurality of products, and to add the second corresponding plurality of products to second corresponding accumulated values to generate a second result matrix.
4. The apparatus of claim 1, wherein the first data elements comprise convolution input elements.
5. The apparatus of claim 4, wherein the second data elements comprise neural network weights.
6. The apparatus of claim 1, wherein the first matrix multiply instruction comprises a first operand to identify the first data elements and a second operand to identify the second data elements.
7. The apparatus of claim 6, wherein the first operand identifies the first data elements in a first one or more registers and the second operand identifies the second data elements in a second one or more registers.
8. The apparatus claim 1, further comprising:
- an instruction fetch unit to fetch the first matrix multiply instruction;
- a decoder to decode the first matrix multiply instruction to generate parallel multiply-add operations; and
- a scheduler to schedule the parallel multiply-add operations for execution by at least a portion of the array of processing elements.
9. The apparatus of claim 1, wherein the first memory device and the second memory device comprise high bandwidth memory (HBM) devices.
10. The apparatus of claim 3, wherein each of the first parallel compute device and the one or more additional parallel compute devices are to access a system memory using a shared address range.
11. The apparatus of claim 10, further comprising coherency logic to ensure coherency of data in the system memory which is shared between the first parallel compute device and the one or more additional parallel compute devices.
12. The apparatus of claim 11, wherein the first program comprises one or more machine learning tasks, wherein separate portions of the one or more machine learning tasks are to be executed by the first parallel compute device and the one or more additional parallel compute devices.
13. An apparatus comprising:
- a compute processor package including a first die and a second die, the first die coupled to a first memory device and the second die coupled to a second memory device;
- a first interconnect to couple the first die and the second die; and
- an interface to couple the compute processor package to one or more additional compute processor packages;
- at least the first die comprising:
- a first scalar register file to store data related to control flow operations;
- first scalar execution circuitry to execute one or more scalar instructions to perform control flow operations in accordance with the data to control execution of an instruction sequence, the control flow operations including program loops, branches, and address calculations, and the instruction sequence including a first matrix multiply instruction;
- a first decoder to decode the instructions of the instruction sequence including the first matrix multiply instruction, the first matrix multiply instruction to specify multiplication of a first matrix by a second matrix, and to specify a first size associated with the first matrix and a second size associated with the second matrix; and
- a first matrix processing unit comprising a first array of processing elements to perform a plurality of parallel fused multiply-accumulate operations in accordance with the first matrix multiply instruction to multiply first data elements of the first matrix by corresponding second data elements of the second matrix to generate a corresponding plurality of products, and to add the plurality of products to corresponding accumulated values to generate a result matrix.
14. The apparatus of claim 13, wherein the second die comprises:
- a second scalar register file to store data related to control flow of a first program or a second program;
- second scalar execution circuitry to execute one or more scalar instructions to perform control flow operations related to execution of the second program in accordance with the data, the control flow operations including program loops, branches, and address calculations;
- a second decoder to decode a second matrix multiply instruction, the second matrix multiply instruction to specify multiplication of a third matrix by a fourth matrix, the second matrix multiply instruction to indicate a third matrix size of the third matrix and a fourth matrix size of the fourth matrix; and
- a second matrix processing unit comprising a second array of processing elements to perform a second plurality of parallel fused multiply-accumulate operations in accordance with the second matrix multiply instruction to multiply third data elements of the third matrix by corresponding fourth data elements of the fourth matrix to generate a second corresponding plurality of products, and to add the second corresponding plurality of products to second corresponding accumulated values to generate a second result matrix.
15. The apparatus of claim 13, wherein the first data elements comprise convolution input elements.
16. The apparatus of claim 15, wherein the second data elements comprise neural network weights.
17. The apparatus of claim 13, wherein the first matrix multiply instruction comprises a first operand to identify the first data elements and a second operand to identify the second data elements.
18. The apparatus of claim 17, wherein the first operand identifies the first data elements in a first one or more registers and the second operand identifies the second data elements in a second one or more registers.
19. The apparatus claim 13, further comprising:
- an instruction fetch unit to fetch the first matrix multiply instruction;
- a decoder to decode the first matrix multiply instruction to generate parallel multiply-add operations; and
- a scheduler to schedule the parallel multiply-add operations for execution by at least a portion of the array of processing elements.
20. The apparatus of claim 13, wherein the first memory device and the second memory device comprise high bandwidth memory (HBM) devices.
21. The apparatus of claim 14, wherein each of the first matrix processing unit and the second matrix processing unit are to access a system memory using a shared address range.
22. The apparatus of claim 21, further comprising coherency logic to ensure coherency of data in the system memory which is shared between the first matrix processing unit and the second matrix processing unit.
23. The apparatus of claim 22, wherein the first program comprises one or more machine learning tasks, wherein separate portions of the one or more machine learning tasks are to be executed by the first matrix processing unit and the second matrix processing unit.
Type: Application
Filed: Oct 26, 2021
Publication Date: Feb 17, 2022
Inventors: Swagath VENKATARAMANI (Tirupur), Dipankar DAS (Pune), Ashish RANJAN (West Lafayette, IN), Subarno BANERJEE (Kolkata), Sasikanth AVANCHA (Malur Taluk), Ashok JAGANNATHAN (Bangalore), Ajaya V. DURG (Austin, TX), Dheemanth NAGARAJ (Bangalore), Bharat KAUL (Bengaluru), Anand RAGHUNATHAN (West Lafayette, IN)
Application Number: 17/511,417
