Abstract: Fluorided silica-coated alumina activator-supports have a bulk density from 0.15 to 0.37 g/mL, a total pore volume from 0.85 to 2 mL/g, a BET surface area from 200 to 500 m2/g, an average pore diameter from 10 to 25 nm, and from 80 to 99% of pore volume in pores with diameters of greater than 6 nm. Methods of making the fluorided silica-coated alumina activator-supports and using the fluorided silica-coated aluminas in catalyst compositions and olefin polymerization processes also are described. Representative ethylene-based polymers produced using the compositions and processes have a melt index of 0.1 to 10 g/10 min and a density of 0.91 to 0.96 g/cm3, and contain from 70 to 270 ppm solid oxide and from 2 to 18 ppm fluorine.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: An electrically conductive and corrosion resistant graphene-based coating composition, including a binder, high-pressure airless-sprayed expanded graphene stacks, carbon fibers, and a dispersing agent, wherein the graphene-based coating composition has an electrical conductivity of at least 2 S/cm and a pull-off adhesion of at least 2 MPa.

Abstract: A method includes retrieving first data from a first data store having a first database topology and second data from a second data store having a second database topology. The first data and the second data are stored in a load data set. The load data set is sorted based on a first identifier field. A first microdatabase is loaded with a first portion of the first data associated with a first value of the first identifier field and a first portion of the second data associated with the first value. A second microdatabase is loaded with a second portion of the first data associated with a second value of the first identifier field and a first portion of the second data associated with the second value. A first key map record for the first microdatabase is generated. A second key map record for the second microdatabase is generated.

Abstract: Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

Abstract: The disclosure provides systems and methods for data analysis of experimental data. The analysis can include reference data that are not directly generated from the present experiment, which reference data may be values of the experimental parameters that were either provided by a user, computed by the system with input from a user, or computed by the system without using any input from a user. Another example of such reference data may be information about the instrument, such as the calibration method of the instrument.

Abstract: Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD), and an opening in the ILD. In an embodiment, a first layer lines the opening, and a second layer lines the first layer. In an embodiment, the second layer comprises a semi-metal or transition metal dichalcogenide (TMD). The integrated circuit structure may further comprise a third layer over the second layer.

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. Other embodiments may be described and/or claimed.

Abstract: Apparatus, system and method to provide switchable coils in a computing device, comprising: a plurality of electrically conductive coils to transfer electromagnetic energy; a sensor coupled to a processor, to select a coil from among the plurality of electrically conductive coils; a switch to energize the selected coil; and a switch controller coupled to the switch and to the processor. In some embodiments, the plurality of coils may comprise an inductive charging interface. Some embodiments may further include a communication interface between the processor to the plurality of electrically conductive coils, the plurality of coils comprising an interface for near-field communications (NFC). The antenna coils may be arranged to provide improved NFC coverage when the computing device is in a respective predetermined physical configuration. Sensors may be used to detect the configuration and switch NFC communications to use a preferred antenna coil for the detected configuration.

Abstract: An example IC device formed using trim patterning as described herein may include a support structure, a first elongated structure (e.g., a first fin or nanoribbon) and a second elongated structure (e.g., a second fin or nanoribbon), proximate to an end of the first elongated structure. An angle between a projection of the first elongated structure on the support structure and an edge of the support structure may be between about 5 and 45 degrees, while an angle between a projection of the second elongated structure on the support structure and the edge of the support structure may be less than about 15 degrees.

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N capacitors coupled to the access transistor. A portion of the capacitors are formed in one or more layers above the access transistor, and a portion of the capacitors are formed in one or more layers below the access transistor. The capacitors in a particular memory unit may be coupled to a single via or to individual vias. In some embodiments, some of the vias are backside vias.

Abstract: IC devices with angled interconnects are disclosed herein. An interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. Angled interconnects may be used to decrease the area of pitch transition regions. Angled interconnects may also be used to decrease the area of pitch offset regions.

Abstract: Described herein are systems and methods that may efficiently detect multi-return light signals. A light detection and ranging system, such as a LIDAR system, may fire a laser beam that may hit multiple objects with a different distance in one line, causing multi-return light signals to be received by the system. Multi-return detectors may be able to analyze the peak magnitude of a plurality of peaks in the return signals and determine a multitude of peaks, such as the first peak, the last peak and the maximum peak. One embodiment to detect the multi-return light signals may be a multi-return recursive matched filter detector. This detector comprises a matched filter, peak detector, centroid calculation and a zeroing out function. Other embodiments may be based on a maximum finder that algorithmically selects the highest magnitude peaks from samples of the return signal and buffers for regions of interests peaks.

Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

Abstract: Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

Abstract: The present invention discloses microtextures for a thin-film evaporation. The microstructure is called as wedged micropillar and a forest of these micropillar helps in maintaining a thin-film of liquid over the heat sink surface through capillary action. The inherent sharp corners of these wedged micropillars drives the liquid filament along the vertical direction and the large mean curvature of the liquid meniscus provides high capillary pumping pressure. At the same time, these microstructures can offer high permeability for liquid flow thereby leading to low viscous pressure loss as compared to the cylindrical microstructured heat sink. As a result of these, the predicted dryout heat flux for thin-film evaporation is more than twice that of the conventional cylindrical microstructures. Also, we have proposed a combined architecture of wedged and cylindrical micropillars for hotspot-targeted cooling application.

Abstract: Described herein are full wafer devices that include passive devices formed in a power delivery structure. Power is delivered to the full wafer device on a backside of the full wafer device. A passive device in a backside layer is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device.

Abstract: Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.